Skip to main content

Compiler Optimizations with DSP-Specific Semantic Descriptions

  • Conference paper
Languages and Compilers for Parallel Computing (LCPC 2002)

Part of the book series: Lecture Notes in Computer Science ((LNTCS,volume 2481))

  • 569 Accesses

Abstract

Due to the specialized architecture and stream-based instruction set, traditional DSP compilers usually yield poor-quality object codes. Lack of an insight into the DSP architecture and the specific semantics of DSP applications, a compiler would have trouble selecting appropriate special instructions to exploit advanced hardware features. In order to extract optimal performance from DSPs, we propose a set of user-specified directives called Digital Signal Processing Interface (DSPI), which can facilitate code generation by relaying DSP specific semantics to compilers. We have implemented a prototype compiler based on the SPAM and SUIF compiler toolkits and integrated the DSPI into the prototype compiler. The compiler is currently targeted to TI’s TMS320C6X DSP and will be extended to a retargetable compiler toolkit for embedded systems and System-on-a-Chip (SoC) platforms. Preliminary experimental results show that by incorporating DSPI directives significant performance improvements can be achieved in several DSP applications.

The work was supported in part by NSC-90-2218-E-007-042, NSC-90-2213-E-007- 074, NSC-90-2213-E-007-075, MOE research excellent project under grant no. 89-EFA04- 1-4, and MOEA research project under grant no. 91-EC-17-A-03-S1-0002 of Taiwan.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

Similar content being viewed by others

References

  1. Ayguade, E., Martorell, X., Labarta, J., Gonzalez, M., Navarro, N.: Exploiting multiple levels of parallelism in openmp: A case study. In: International Conference on Parallel Processing, pp. 172–180 (1999)

    Google Scholar 

  2. Batten, D., Jinturkar, S., Glossner, J., Schulte, M., D’Arcy, P.: A new approach to dsp intrinsic functions. In: Proceedings of the Hawaii International Conference on System Sciences, January 2000, pp. 908–918 (2000)

    Google Scholar 

  3. Batten, D., Jinturkar, S., Glossner, J., Schulte, M., Peri, R., D’Arcy, P.: Interaction between optimizations and a new type of dsp intrinsic function. In: Proceedings of the International Conference on Signal Processing Applications and Technology (ICSPAT 1999) (November 1999)

    Google Scholar 

  4. Bozkus, Z., Choudhary, A., Fox, G., Haupt, T., Ranka, S.: Fortran 90d/hpf compiler for distributed memory mimd computers: design, implementation and performance results. In: Proceedings of Supercomputing 1993, November 1993, pp. 351–360 (1993)

    Google Scholar 

  5. Chang, R.G., Chuang, T.R., Lee, J.-K.: Efficient support of parallel sparse computation for array intrinsic functions of fortran 90. In: Proceedings of ACM International Conference on Supercomputing (July 1998)

    Google Scholar 

  6. Chang, R.-G., Li, J.-S., Chuang, T.-R., Lee, J.K.: Probabilistic inference schemes for sparsity structures of fortran 90 array intrinsics. In: Proceedings of the 2001 International Conference on Parallel Processing (September 2001)

    Google Scholar 

  7. Chen, D., Zhao, W., Ru, H.: Design and implementation issues of intrinsic functions for embedded dsp processors. In: Proceedings of the ACM SIGPLAN International Conference on Signal Processing Applications and Technology (ICSPAT 1997), September 1997, pp. 505–509 (1997)

    Google Scholar 

  8. Ghazal, N., Newton, R., Rabaey, J.: Predicting performance potential of modern dsps. In: Proceedings of IEEE/ACM Design Automation Conference (DAC) (June 2000)

    Google Scholar 

  9. SPAM Research Group. SPAM Compiler User’s Manual (September 1997), http://www.ee.princeton.edu/spam/

  10. Stanford Compiler Group. The SUIF Library (1994), http://suif.stanford.edu/suif/suif1/docs/suiftoc.html

  11. Hadjiyiannis, G., Hanono, S., Devadas, S.: Isdl: An instruction set description language for retargetability. In: Proceedings of ACM/IEEE Design Automation Conference (October 1997)

    Google Scholar 

  12. Halambi, A., Grun, P., Ganesh, V., Khare, A., Dutt, N., Nicolau, A.: Expression: A language for architecture exploration through compiler/ simulator retargetability. In: Proceedings of Design, Automation, and Test in Europe conference, DATE (1999)

    Google Scholar 

  13. Hwang, G.-H., Lee, J.K., Ju, D.-C.: Integrating automatic data alignment and array operation synthesis to optimize data parallel programs. In: Huang, C.-H., Sadayappan, P., Sehr, D. (eds.) LCPC 1997. LNCS, vol. 1366. Springer, Heidelberg (1998)

    Google Scholar 

  14. Hwang, G.-H., Lee, J.K., Ju, R.D.-C.: A functioncomposition approach to synthesize fortran 90 array operations. Journal of Parallel and Distributed Computing 54, 1–47 (1998)

    Article  MATH  Google Scholar 

  15. Hwang, Y.-S., Chen, P.-S., Lee, J.-K., Ju, R.: Probabilistic points-to analysis. In: Proceedings of the 15th International Workshop on Languages and Compilers for Parallel Computing (LCPC 2001) (August 2001)

    Google Scholar 

  16. Texas Instruments Incorporated. TMS320C62x/C67x CPU and Instruction Set. Texas Instuments Incorporated (1998), http://www.ti.com/sc/psheets/spru189d/spru189d.pdf

  17. Jersak, M., Willems, M.: Fixed-point extended c compiler allows more efficient high-level programming of fixed-point dsps. In: Proceedings of the International Conference on Signal Processing Applications and Technology (ICSPAT 1998) (October 1998)

    Google Scholar 

  18. Glossner, J., Routenberg, D., Hokenek, E., Moudgill, M., Schulte, M., Balzola, P., Vassiliadis, S.: Towards a very high bandwidth wireless handheld device. Technical report, Sandbridge Technologies, Inc., White Paper (2001)

    Google Scholar 

  19. Krepp, B.: Dsp-oriented extension to ansi c. In: Proceedings of the International Conference on Signal Processing Applications and Technology (ICSPAT 1997), pp. 658–664 (1997)

    Google Scholar 

  20. Kulkarni, A.K., Dube, A.: Benchmarking code generation methodologies for programmable digital signal processors (April 1997)

    Google Scholar 

  21. Leary, K., Waddington, W.: Dsp/c: a standard high level language for dsp aad numeric processing. In: Proceedings of the International Conference on Acoustic, Speech, and Signal Processing, pp. 1065–1068 (1990)

    Google Scholar 

  22. Lee, C., Lee, J.K., Hwang, T., Tsai, S.-C.: Compiler optimization on instruction scheduling for low power. In: Proceedings of the 13th International Symposium on System Synthesis, September 2000, pp. 55–60 (2000)

    Google Scholar 

  23. You, Y.-P., Lee, C.-R., Lee, J.-K., Shih, W.-K.: Real-time task scheduling for dynamically variable voltage processors. In: Proceedings of IEEE Workshop on Power Management for Real-Time and Embedded Systems (May 2001)

    Google Scholar 

  24. Zivojnovic, V., Pees, S., Meyr, H.: Lisa – machine description language and generic machine model for hw/sw co-design. In: Proceedings of IEEE Workshop on VLSI Signal Processing (October 1996)

    Google Scholar 

  25. Zivojnovic, V., Velarde, J.M., Schlager, C., Meyr, H.: Dspstone, a dsp-oriented benchmarking methodology - final report. Technical report, Aachen University, Germany, Technical Report (August 1994)

    Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Editor information

Editors and Affiliations

Rights and permissions

Reprints and permissions

Copyright information

© 2005 Springer-Verlag Berlin Heidelberg

About this paper

Cite this paper

Lin, YC., Hwang, YS., Lee, J.K. (2005). Compiler Optimizations with DSP-Specific Semantic Descriptions. In: Pugh, B., Tseng, CW. (eds) Languages and Compilers for Parallel Computing. LCPC 2002. Lecture Notes in Computer Science, vol 2481. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11596110_6

Download citation

  • DOI: https://doi.org/10.1007/11596110_6

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-30781-5

  • Online ISBN: 978-3-540-31612-1

  • eBook Packages: Computer ScienceComputer Science (R0)

Publish with us

Policies and ethics