Abstract
We purposed a new Network on Chip (NoC) architecture called Hierarchical Graph. The most interesting feature of this novel architecture is its simple implementation process. Furthermore, the flexible structure of this topology makes it suitable for use in application specified chips. To benchmark the suggested architecture with existing ones, basic models of physical implementation have been extracted and simulated using NS-2. The results compared with the common used architecture Mesh show that HG has better performance, especially in local traffics and high loads.
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References
ITRS. International technology roadmap for semiconductors - 2004 edition, http://public.itrs.net/
Benini, L., De Micheli, G.: Networks on Chip: A New SoC paradigm. IEEE Computer 35(1), 70–78 (2002)
Day, J.D., Zimmermann, H.: The OSI reference model. In: Proceedings of the IEEE, pp. 1334–1340 (December 1983)
Kumar, S., et al.: A Network on Chip Architecture and Design Methodology. In: IEEE Computer Society Annual Symposium on VLSI, Pittsburgh, Pennsylvania, USA (April 2002)
Sun, Y.-R., Kumar, S., Jantsch, A.: Simulation and Evaluation for a Network on Chip Architecture Using Ns-2. In: Proceedings of 20th NORCHIP conference, Copenhagen (November 2002)
Ngo, V.-D., Choi, H.-W.: On Chip Network: Topology design and evaluation using NS2
Wiklund, D., Sathe, S., Liu, D.: Network on chip simulations for benchmarking. In: Proceedings of the International workshop on SoC for real-time applications, Banff, Canada (July 2004)
Kavaldjiev, N., Smit, G.J.M., Jansen, P.G.: A Virtual Channel Router for On-chip Networks. In: Proceedings of IEEE International SOC Conference, Santa ClaraSep, California (2004)
The network simulator - NS-2, http://www.isi.edu/nsnam/ns/
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© 2005 Springer-Verlag Berlin Heidelberg
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Vahdatpour, A., Tavakoli, A., Falaki, M.H. (2005). Hierarchical Graph: A New Cost Effective Architecture for Network on Chip. In: Yang, L.T., Amamiya, M., Liu, Z., Guo, M., Rammig, F.J. (eds) Embedded and Ubiquitous Computing – EUC 2005. EUC 2005. Lecture Notes in Computer Science, vol 3824. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11596356_33
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DOI: https://doi.org/10.1007/11596356_33
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-30807-2
Online ISBN: 978-3-540-32295-5
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