Abstract
The hit ratio of the first level cache is one of the most important factors in determining the performance of embedded computer systems. Prefetching from lower level memory structure is one of the techniques for improving the hit ratio of the first level cache. This paper proposes an effective prefetch scheme for the first level instruction cache by exploiting cache history information. The proposed scheme utilizes two factors to improve the prefetch efficiency: the disparity of block size between memory hierarchies and continuous same page hits. According to our simulations, the proposed prefetching scheme improves the performance by up to 6.3%.
This work was supported by Brain Korea 21.
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© 2005 Springer-Verlag Berlin Heidelberg
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Shin, S.H., Kim, C.H., Jhon, C.S. (2005). An Effective Instruction Cache Prefetch Policy by Exploiting Cache History Information. In: Yang, L.T., Amamiya, M., Liu, Z., Guo, M., Rammig, F.J. (eds) Embedded and Ubiquitous Computing – EUC 2005. EUC 2005. Lecture Notes in Computer Science, vol 3824. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11596356_9
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DOI: https://doi.org/10.1007/11596356_9
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-30807-2
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