Abstract
The hit ratio of the first level cache is one of the most important factors in determining the performance of embedded computer systems. Prefetching from lower level memory structure is one of the techniques for improving the hit ratio of the first level cache. This paper proposes an effective prefetch scheme for the first level instruction cache by exploiting cache history information. The proposed scheme utilizes two factors to improve the prefetch efficiency: the disparity of block size between memory hierarchies and continuous same page hits. According to our simulations, the proposed prefetching scheme improves the performance by up to 6.3%.
This work was supported by Brain Korea 21.
Preview
Unable to display preview. Download preview PDF.
Similar content being viewed by others
References
Smith, A.: Cache memories. ACM Computing Surveys 14, 473–530 (1982)
Dahlgren, F., Dubois, M., Stenström, P.: Fixed and adaptive sequential prefetching in shared memory multiprocessors. In: International Conference on Parallel Processing, pp. 56–63 (1993)
Jouppi, N.P.: Improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers. In: International Symposium on Computer Architecture, pp. 364–373 (1990)
Reinman, G., Calder, B., Austin, T.: Fetch directed instruction prefetching. In: International Symposium on Microarchitecture, pp. 16–27 (1999)
Zhang, Y., Haga, S., Barua, R.: Execution history guided instruction prefetching. In: International Conference on Supercomputing, pp. 199–208 (2002)
Batcher, K., Walker, R.: Cluster miss prediction with prefetch on miss for embedded cpu instruction caches. In: International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, pp. 24–34 (2004)
Hsu, W.C., Smith, J.E.: A performance study of instruction cache prefetching methods. IEEE Transactions on Computers 47, 497–508 (1998)
Lee, C., Potkonjak, M., Mangione-Smith, W.H.: Mediabench: A tool for evaluating and synthesizing multimedia and communicatons systems. In: International Symposium on Microarchitecture, pp. 330–335 (1997)
SPEC: (SPEC CPU2000 Benchmarks), http://www.specbench.org
Burger, D., Austin, T.M., Bennett, S.: Evaluating future microprocessors: the simplescalar tool set. Technical Report TR-1308, Univ. of Wisconsin-Madison Computer Sciences Dept. (1997)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2005 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Shin, S.H., Kim, C.H., Jhon, C.S. (2005). An Effective Instruction Cache Prefetch Policy by Exploiting Cache History Information. In: Yang, L.T., Amamiya, M., Liu, Z., Guo, M., Rammig, F.J. (eds) Embedded and Ubiquitous Computing – EUC 2005. EUC 2005. Lecture Notes in Computer Science, vol 3824. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11596356_9
Download citation
DOI: https://doi.org/10.1007/11596356_9
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-30807-2
Online ISBN: 978-3-540-32295-5
eBook Packages: Computer ScienceComputer Science (R0)