Skip to main content

On Using Locking Caches in Embedded Real-Time Systems

  • Conference paper
Embedded Software and Systems (ICESS 2005)

Part of the book series: Lecture Notes in Computer Science ((LNTCS,volume 3820))

Included in the following conference series:

  • 990 Accesses

Abstract

Cache memories are crucial to obtain high performance on contemporary processors. However, they have been traditionally avoided in embedded real-time systems due to their lack of determinism. Unfortunately, most of the techniques to attain predictability on caches are complex to apply, precluding their use on real applications. This work reviews several techniques developed by the authors to use cache memories in “real” embedded real-time systems, with the ease of use in mind. Those techniques are based on a locking cache, which offers a very predictable behaviour. Both static and dynamic use are proposed as well as the algorithms and methods required to make the schedulability analysis using two different scheduling policies. Also proposed is a genetic algorithm that finds, within acceptable computational cost, the sub-optimal set of instructions that must be preloaded in cache. Finally, a set of statistical analyses compares the locking cache versus a conventional one.

Work partially supported by Ministerio de Educación y Ciencia, Dirección General de Investigación under project DPI2003-08320-C02-01.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

Similar content being viewed by others

References

  1. Audsley, A.N., Burns, A., Richardson, M., Tindell, K.: Applying new scheduling theory to static priority pre-emptive scheduling. Software Engineering Journal 8, 284–292 (1993)

    Article  Google Scholar 

  2. Busquets-Mataix, J.V., Wellings, A.J., Serrano-Martin, J.J., Ors-Carot, R., Gil, P.: Adding instruction cache effect to an exact schedulability analysis of preemptive real-time systems. In: Proc. of the Eighth Euromicro Workshop on Real-Time Systems, pp. 271–276. IEEE Computer Society Press, Los Alamitos (1996)

    Chapter  Google Scholar 

  3. Healy, C.A., Arnold, R.D., Mueller, F., Harmon, M.G., Walley, D.B.: Bounding pipeline and instruction cache performance. IEEE Trans. Comput. 48, 53–70 (1999)

    Article  Google Scholar 

  4. Holland, J.H.: Adaptation in Natural and Artificial Systems. MIT Press, Cambridge (1992)

    Google Scholar 

  5. Kirk, D.B.: SMART (Strategic Memory Allocation for Real-Time) cache design. In: Proc. of the 10th IEEE Real-Time Systems Symposium, pp. 229–237. IEEE Computer Society Press, Los Alamitos (1989)

    Google Scholar 

  6. Lee, C.-G., Hahn, J., Seo, Y.-M., Min, S.L., Ha, R., Hong, S., Park, C.Y., Lee, M.C., Kim, S.: Enhanced analysis of cache-related preemption delay in fixed-priority preemptive scheduling. In: Proc. of the 18th IEEE Real-Time Systems Symposium (RTSS 1997), pp. 187–198. IEEE Computer Society Press, Los Alamitos (1997)

    Google Scholar 

  7. Li, Y.-T.S., Malik, S., Wolfe, A.: Cache modeling for real-time software: beyond direct mapped instruction caches. In: Proc. of the 17th IEEE Real-Time Systems Symposium (RTSS 1996), pp. 254–263. IEEE Computer Society Press, Los Alamitos (1996)

    Chapter  Google Scholar 

  8. Lim, S.-S., Bae, Y.H., Jang, G.T., Rhee, B.-D., Min, S.L., Park, C.Y., Shin, H., Park, K., Moon, S.-M., Kim, C.S.: An accurate worst case timing analysis for RISC processors. IEEE Trans. Softw. Eng. 21, 593–604 (1995)

    Article  Google Scholar 

  9. Mart Campoy, A., Pérez Jiménez, A., Perles Ivars, A., Busquets Mataix, J.V.: Using genetic algorithms in content selection for locking-caches. In: Proc. of the IASTED International Symposia Applied Informatics, pp. 271–276. Acta Press, Innsbruck (2001)

    Google Scholar 

  10. Marti Campoy, A., Perles Ivars, A., Busquets Mataix, J.V.: Static Use of Locking Caches in Multitask Preemptive Real-Time Systems. In: Proceedings of the IEEE/IEE Real-Time Embedded Systems Workshop (Satellite of the 22nd IEEE Real-Time Systems Symposium), London, UK (December 2001)

    Google Scholar 

  11. Marti Campoy, A., Perles Ivars, A., Busquets Mataix, J.V.: Dynamic Use of Locking Caches in Multitask, Preemptive Real-Time Systems. In: Proceedings of the 15th Triennial World Congress of the International Federation of Automatic Control, July 2002. Elsevier Science, Barcelona (2002)

    Google Scholar 

  12. Ripoll, I., Crespo, A., Mok, A.: Improvement in feasibility testing for real-time tasks. Journal of Real-Time Systems 11, 19–40 (1996)

    Article  Google Scholar 

  13. Shaw, A.C.: Reasoning about time in higher-level language software. IEEE Trans. Softw. Eng. 15, 875–889 (1989)

    Article  Google Scholar 

  14. Tamura, E., Rodríguez, F., Busquets-Mataix, J.V., Martí Campoy, A.: High Performance Memory Architectures with Dynamic Locking Cache for Real-Time Systems. In: Proc. of the Work-In-Progress session of the 16th Euromicro Conference on Real-Time Systems. Available as Technical Report from the University of Nebraska-Lincoln, Department of Computer Science and Engineering (TRUNL-CSE-2004-0010), 1–4 (2004)

    Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Editor information

Editors and Affiliations

Rights and permissions

Reprints and permissions

Copyright information

© 2005 Springer-Verlag Berlin Heidelberg

About this paper

Cite this paper

Campoy, A.M., Tamura, E., Sáez, S., Rodríguez, F., Busquets-Mataix, J.V. (2005). On Using Locking Caches in Embedded Real-Time Systems. In: Yang, L.T., Zhou, X., Zhao, W., Wu, Z., Zhu, Y., Lin, M. (eds) Embedded Software and Systems. ICESS 2005. Lecture Notes in Computer Science, vol 3820. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11599555_17

Download citation

  • DOI: https://doi.org/10.1007/11599555_17

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-30881-2

  • Online ISBN: 978-3-540-32297-9

  • eBook Packages: Computer ScienceComputer Science (R0)

Publish with us

Policies and ethics