Abstract
System-on-chip (SoC) designs provide integrated solutions to challenging design problems in the telecommunications, multimedia, and so on. Present and future SoC are designed using pre-existing components which we call cores. Communication between the cores will become a major bottleneck for system performance as standard hardwired bus-based communication architectures will be inefficient in terms of throughput, latency and power consumption. To solve this problem, a packet switched platform that considers the delay and reliability issues of wires so called Network-on-Chip (NoC) has been proposed. In this paper, we present interconnected network topologies and analyze their performances with a particular application under bandwidth constrains. Then we compare the performances among different ways of mapping the cores onto a Mesh NoC architecture. The comparison between Mesh and Fat-Tree topology is also presented. These evaluations are done by utilizing NS-2, a tool that has been widely used in the computer network design.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Guerrier, P., Grenier, A.: A generic architecture for on-chip packet-switched interconnection. In: Design automation and test in Europe conference, pp. 250–256 (August 2000)
Horowitz, M.A., et al.: The future of wires. Proceeding of IEEE 89(4), 490–504 (2001)
Benini, L., De Micheli, G.: Networks On Chips: A new SoC paradigm. IEEE computer (January 2002)
Petrini, F., Vanneschi, M.: Network performance under Physical Constrain. In: Proceedings of International Conference on Parallel Processing, pp. 34–43 (August 1997)
Leiserson, C.E.: Fat Trees: Universal networks for hardware efficient supercomputing. IEEE Transactions on Computer 34, 890–900 (1985)
Kariniemi, H., Nurmi, J.: New adaptive routing algorithm for extended generalized fat trees on-chip. In: Proceedings of International Symposium on System-on-Chip, pp. 113–118 (November 2003)
Pande, P.P., Grecu, C., Ivanov, A., Saleh, R.: Design of a switch for network on chip applications. In: Proceedings of the 2003 International Symposium on Circuits and Systems, pp, May 2003, vol. 5, pp. V-217 –V-220 (2003)
Van der Tol, E.B., Jaspers, E.G.T.: Mapping of MPEG-4 Decoding on a Flexible Architecture Platform. In: SPIE 2002, pp. 1–13 (January 2002)
Murali, S., De Micheli, G.: Bandwidth Constrained Mapping of Cores onto NoC Architectures. In: Proc. Conf. DATE 2004 (2004)
Hu, J., Marculescu, R.: Energy-Aware Mapping for Tile-Based NoC Architecture under Performance Constraints. In: Proc. Asia and South Pacific Design Automation Conf., pp. 233–239 (January 2003)
Sun, Y.-R., Kumar, S., Jantsch, A.: Simulation and Evaluation for a Network on Chip Architecture Using NS-2. In: Proceeding of 20th IEEE Norchip Conference (November 2002)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2005 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Nguyen, HN., Ngo, VD., Choi, HW. (2005). Realization of Video Object Plane Decoder on On-Chip Network Architecture. In: Yang, L.T., Zhou, X., Zhao, W., Wu, Z., Zhu, Y., Lin, M. (eds) Embedded Software and Systems. ICESS 2005. Lecture Notes in Computer Science, vol 3820. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11599555_26
Download citation
DOI: https://doi.org/10.1007/11599555_26
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-30881-2
Online ISBN: 978-3-540-32297-9
eBook Packages: Computer ScienceComputer Science (R0)