Abstract
In embedded world, many researchers have begun to examine Simultaneous Multithreading (SMT) and Chip Multiprocessing (CMP) for various demands. SMT and CMP both make a chip to achieve greater throughput. But the power, chip size and thermal features are also important for embedded system. In this paper we compare the design space of both architecture. As simulation results shown, although extending wide-issue processor into SMT has the advantage of small design changes, high hardware resource efficiency and high throughput, CMP presents better scalability in raw performance and power metric under heavy multithreaded workload than SMP. CMP integrates several similar processor in a single chip, so it can’t uses the chip area efficiently like SMT. And the chip area limits will prevent the CMP from equipping a large L2 cache, which will hurt the performance of memory-bound application. The evaluation also points out the design problem and possible solution for power, chip size and thermal efficiency in CMP and SMT.
Preview
Unable to display preview. Download preview PDF.
Similar content being viewed by others
References
Burger, D., Goodman, J.R.: Billion-Transistor Architectures: There and Back Again. IEEE Computer 37(3), 22–27 (2004)
Tullsen, D.M., Eggers, S.J., Levy, H.M.: Simultaneous Multithreading: Maximumizing On-Chip Parallelism. In: Proceedings of ISCA 22nd, pp. 392–403 (1995)
Hammond, L., Nayfeh, B.A., Olukotum, K.: A Single-Chip Multiprocessor. In: IEEE Computer Special Issue on Billion-Transistor Processors (September 1997)
Ungerer, T., Robic, B.: A Survey of Processors with Explicit Multithreading. ACM Computing Surveys 35(1), 29–63 (2003)
Sasanka, R., Adve, S.V., Debes, E., Chen, Y.K.: Energy Efficiency of CMP and SMT Architectures for Multimedia workloads. In: UIUC CS Technical Report UIUCDCS-R-2003-2325 (2003)
Sasanka, R., Adve, S.V., Debes, E., Chen, Y.K., Debes, E.: The Energy Efficiency of CMP vs. SMT for Multimedia workloads. In: ICS (2004)
Burns, J., Gaudiot, J.L.: Area and System Clock Effects on SMT/CMP Processors. In: PACT (2000)
Kaxiras., S., Narlikar, G., Berenbaum, A.D., Hu, Z.: Comparing Power Consumption of and SMT and a CMP DSP for mobile phone Workloads. In: CASES (2001)
Li, Y., Brooks, D., Hu, Z., Skadron, K.: Performance, Energy, and Thermal Considerations for SMT and CMP Architectures. In: HPCA (2005)
Brooks, D., Tiwari, V., Martonosi, M.: Wattch: A Framework for Architectureal-Level Power Analysis and Optimizations. In: ISCA27 (2000)
SIA. International Technology Roadmap for Semiconductors (2004)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2005 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Tang, Y., Deng, K., Zhou, X. (2005). The Design Space of CMP vs. SMT for High Performance Embedded Processor. In: Yang, L.T., Zhou, X., Zhao, W., Wu, Z., Zhu, Y., Lin, M. (eds) Embedded Software and Systems. ICESS 2005. Lecture Notes in Computer Science, vol 3820. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11599555_6
Download citation
DOI: https://doi.org/10.1007/11599555_6
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-30881-2
Online ISBN: 978-3-540-32297-9
eBook Packages: Computer ScienceComputer Science (R0)