Abstract
This paper presents a case study of the application of assertion-based verification to a multi-million-gate design of the SpaceCAKE architecture with shared L2 cache. SpaceCAKE L2 cache is highly configurable and implements Distributed Shared Memory (DSM) architecture. This paper discusses the issues faced during the functional verification of this architecture. A number of techniques are employed to verify the design. The paper serves as a case study for verification of such a complex architecture. A description of the different techniques that were used to verify this architecture and an assessment of using a comprehensive coverage-driven verification plan that exploits the benefits of the traditional simulation techniques through the use of assertions is presented. We have found that the tools, currently provided by the market, for assertion-based static verification approach need more maturity. A 50% reduction in debug time has been achieved through the use of assertions.
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References
Stravers, P., Hoogerbrugge, J.: Homogeneous Multiprocessing and the Future of Silicon Design Paradigms. In: Proceedings of the IEEE International Symposium on VLSI technology, Systems and Applications, April 2001, pp. 184–187 (2001)
Stravers, P.: Homogeneous Multiprocessing for the Masses. In: IEEE Workshop on Embedded Systems for Real-Time Multimedia, September 2004, p. 3 (2004)
Property Specification Language Version 1.1, Reference Manual, Accellera (June 2004)
Open Verification Library, Assertion Monitor Reference Manual, Accellera (June 2003)
Philips Semiconductors. CoReUse 3.2.1 Memory Transaction Level (MTL) Protocol Specifications (September 2002)
Philips Semiconductors. CoReUse 3.1.5 Device Transaction Level (DTL) Protocol Specifications (December 2001)
AMBA Advanced eXtensible Protocol v1.0 Specification
Cadence Specman Elite v4.3.4
Hennessy, J., Patterson, D.: Computer Architecture and Organization, 3rd edn. Morgan Kaufmann Publishers, San Francisco (2003)
Sloane, N.J.A.: A Library of Orthogonal Arrays. Information Sciences Research Center, AT&T Shannon Labs.(9 Augest 2001)
Jenny Tool, http://burtleburtle.net/bob/math/jenny.html
Incisive Static Assertion Checking Guide, Product Version 5.1 (October 2003)
Kantrowitz, M., Noack, L.M.: I’m Done Simulating: Now What? Verification Coverage Analysis and Correctness Checking of the DECchip 21164 Alpha Microprocessor. In: Proceedings of the 33rd Design Automation Conference, June 1996, pp. 325–330 (1996)
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© 2006 Springer-Verlag Berlin Heidelberg
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Kulkarni, M., Bommi J., B. (2006). Assertion-Based Verification for the SpaceCAKE Multiprocessor – A Case Study. In: Ur, S., Bin, E., Wolfsthal, Y. (eds) Hardware and Software, Verification and Testing. HVC 2005. Lecture Notes in Computer Science, vol 3875. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11678779_4
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DOI: https://doi.org/10.1007/11678779_4
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-32604-5
Online ISBN: 978-3-540-32605-2
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