Abstract
Recent study shows that a further speedup can be achieved by RISC-based extensible processors if the incorporated custom functional units (CFUs) can execute functions with more than two inputs and one output. However, mechanisms to execute multiple-input, multiple-output (MIMO) custom functions in a RISC processor have not been addressed. This paper proposes an extension for single-issue RISC processors based on a CFU that can execute custom functions with up to six inputs and three outputs. To minimize the change to the core processor, we maintain the operand bandwidth of two inputs, one output per cycle and transfer the extra operands and results using repeated custom instructions. While keeping such an limit sacrifices some speedup, our experiments show that the MIMO extension can still achieve an average 51% increase in speedup compared to a dual-input, single-output (DISO) extension and an average 27% increase in speedup compared to a multiple-input, single-output (MISO) extension.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Altera Corp., NIOS II Custom Instruction User Guide (2005)
Yu, P., Mitra, T.: Scalable Custom Instructions Identification for Instruction-Set Extensible Processors. In: Proceedings of the International Conference on Compilers, Architectures, and Synthesis for Embedded Systems, Washington, DC (September 2004)
Atasu, K., Pozzi, L., Ienne, P.: Automatic Application-Specific Instruction-Set Extensions Under Microarchitectural constraints. In: 40st ACM/IEEE Design Automation Conference (DAC) (2003)
Hauser, J.R., Wawrzynek, J.: Grap: A MIPS Processor with A Reconfigurable Coprocessor. In: Proceedings of the 5th IEEE Symposium on Field-Programmable Custom Computing Machines, Napa Valley, Calif. (April 1997)
Kastrup, B., Bink, A., Hoogerbrugge, J.: ConCISe: A Compiler-Driven CPLD-based Instruction Set Accelerator. In: Proceedings of the 7th IEEE Symposium on Field-Programmable Custom Computing Machines, Napa Valley, Calif. (April 1999)
Ienne, P., Pozzi, L., Vuletic, M.: On the Limits of Processor Specialisation by Mapping Dataflow Sections on Ad-hoc Functional Units. Technical Report 01/376, Swiss Federal Institute of Technology Lausanne, Computer Science Department (December 2001)
Xilinx Inc., PowerPC Processor Reference Guide (2003)
Cong, J., Fan, Y., Han, G., Jagannathan, A., Reinman, G., Zhang, Z.: Instruction Set Extension with Shadow Registers for Configurable Processors. In: Proceedings of the ACM International Symposium on Field-Programmable Gate Arrays (February 2005)
Biswas, P., Banerjee, S., Dutt, N.D., Pozzi, L., Ienne, P.: ISEGEN: Generation of High-Quality Instruction Set Extensions by Iterative Improvement. Design Automation and Test in Europe (DATE) (2005)
Yu, P., Mitra, T.: Characterizing Embedded Applications for Instruction-Set Extensible Processors. In: 41st ACM/IEEE Design Automation Conference (DAC) (June 2004)
Razdan, R., Smith, M.D.: A High-Performance Microarchitecture with Hardware-Programmable Functional Units. In: Proceedings of the 27th Annual International Symposium on Microarchitecture (MICRO-27) (November 1994)
SimpleScalar LLC, http://www.simplescalar.com
Kuzmanov, G., Gaydadjiev, G., Vassiliadis, S.: The MOLEN Processor Prototype. In: FCCM 2004 (2004)
MediaBench, http://cares.icsl.ucla.edu/MediaBench/
Kane, G., Heinrich, J.: MIPS RISC Architecture. Prentice-Hall, Englewood Cliffs (1992)
Altera Corp.: Nios II Processor Reference Handbook (2005)
Xilinx Inc.: MicroBlaze Processor Reference Guide (2005)
Guo, Z., Najjar, W., Vahid, F., Vissers, K.: A Quantitative Analysis of The Speedup Factors of FPGAs over Processors. In: Proceeding of the 2004 ACM/SIGDA 12th international Symposium on Field programmable Gate Arrays, Monterey, California, USA (February 2004)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2006 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Chen, X., Maskell, D.L. (2006). M2E: A Multiple-Input, Multiple-Output Function Extension for RISC-Based Extensible Processors. In: Grass, W., Sick, B., Waldschmidt, K. (eds) Architecture of Computing Systems - ARCS 2006. ARCS 2006. Lecture Notes in Computer Science, vol 3894. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11682127_14
Download citation
DOI: https://doi.org/10.1007/11682127_14
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-32765-3
Online ISBN: 978-3-540-32766-0
eBook Packages: Computer ScienceComputer Science (R0)