Abstract
This paper presents a novel low power design methodology for dynamic CMOS circuits in order to improve the design trade-off between power and speed. It also discusses a new design methodology of power reduction techniques for high-performance chips. As confirmed through the experiment, we are maximizing the performance of the chip in terms of speed and power. The simulation results of the proposed method are compared and possible improvements and applications are discussed.
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© 2006 Springer-Verlag Berlin Heidelberg
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Jeong, T.T., Ambler, A.P. (2006). Design Trade-Offs and Power Reduction Techniques for High Performance Circuits and System. In: Gavrilova, M.L., et al. Computational Science and Its Applications - ICCSA 2006. ICCSA 2006. Lecture Notes in Computer Science, vol 3984. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11751649_58
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DOI: https://doi.org/10.1007/11751649_58
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-34079-9
Online ISBN: 978-3-540-34080-5
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