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BDD-Based Hardware Verification

  • Conference paper
Formal Methods for Hardware Verification (SFM 2006)

Part of the book series: Lecture Notes in Computer Science ((LNPSE,volume 3965))

Abstract

This chapter overviewes Binary Decision Diagrams (BDDs) and their application in Formal Hardware Verification. BDDs are first described as a representation formalism for Boolean functions. BDDs are directed acyclic graphs, deriving their efficiency from canonicity, and from their ability to be exponentially more compact, in terms of node count, than alternative Boolean representations. The chapter introduces the main BDD operators, in terms of recursive graph manipulation functions. Some of the most succesful Formal Verification techniques, based on BDD engines, are then reported. The description is limited to Reduced Ordered BDDs (ROBDDs), which, albeight being just one among several decomposition types, are the most widely used and the most general one.

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Author information

Authors and Affiliations

  1. Dip. di Automatica e Informatica, Politecnico di Torino, Turin, Italy

    Gianpiero Cabodi & Marco Murciano

Authors
  1. Gianpiero Cabodi
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  2. Marco Murciano
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Editor information

Editors and Affiliations

  1. Istituto di Scienze e Tecnologie dell’Informazione, Università di Urbino “Carlo Bo”, Italy

    Marco Bernardo

  2. FBK-IRST, Povo, Trento, Italy

    Alessandro Cimatti

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© 2006 Springer-Verlag Berlin Heidelberg

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Cabodi, G., Murciano, M. (2006). BDD-Based Hardware Verification. In: Bernardo, M., Cimatti, A. (eds) Formal Methods for Hardware Verification. SFM 2006. Lecture Notes in Computer Science, vol 3965. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11757283_4

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  • DOI: https://doi.org/10.1007/11757283_4

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-34304-2

  • Online ISBN: 978-3-540-34305-9

  • eBook Packages: Computer ScienceComputer Science (R0)

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