Skip to main content
SpringerLink
Log in
Book cover

International School on Formal Methods for the Design of Computer, Communication and Software Systems

SFM 2006: Formal Methods for Hardware Verification pp 108–143Cite as

SAT-Based Verification Methods and Applications in Hardware Verification

  • Conference paper

Part of the book series: Lecture Notes in Computer Science ((LNPSE,volume 3965))

Abstract

Verification methods based on Boolean Satisfiability (SAT) have emerged as a promising alternative to BDD-based symbolic model checking methods. This paper provides a tutorial on various SAT-based verification methods we have developed for verifying large hardware designs. We focus separately on methods for finding bugs and for finding proofs for correctness properties, along with highlighting the many common themes that benefit these methods. We also describe practical experiences with these methods implemented in our verification platform called VeriSol (formerly DiVer), which has been used successfully in industry practice.

This is a preview of subscription content, log in via an institution.

Chapter
USD   29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD   39.99
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD   54.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Learn about institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. Clarke, E.M., Grumberg, O., Peled, D.: Model Checking. MIT Press, Cambridge (1999)

    Google Scholar 

  2. Burch, R., Clarke, E.M., Long, D.E., McMillan, K.L., Dill, D.: Symbolic model checking for sequential circuit verification. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 13(4), 401–424 (1994)

    Article  Google Scholar 

  3. McMillan, K.L.: Symbolic Model Checking: An Approach to the State Explosion Problem. Kluwer Academic Publishers, Dordrecht (1993)

    Book  Google Scholar 

  4. Bryant, R.E.: Graph-based algorithms for Boolean function manipulation. IEEE Transactions on Computers C-35(8), 677–691 (1986)

    Article  MATH  Google Scholar 

  5. Marques-Silva, J.P., Sakallah, K.A.: GRASP: A Search Algorithm for Propositional Satisfiability. IEEE Transactions on Computers 48, 506–521 (1999)

    Article  MathSciNet  Google Scholar 

  6. Moskewicz, M., Madigan, C., Zhao, Y., Zhang, L., Malik, S.: Chaff: Engineering an Efficient SAT Solver. In: Proceedings of Design Automation Conference (2001)

    Google Scholar 

  7. Zhang, H.: SATO: An efficient propositional prover. In: Proceedings of International Conference on Automated Deduction, pp. 272–275 (1997)

    Google Scholar 

  8. Goldberg, E., Novikov, Y.: BerkMin: A Fast and Robust SAT-Solver. In: Proceedings of Conference on Design Automation & Test Europe (DATE), pp. 142–149 (2002)

    Google Scholar 

  9. Zhang, L., Malik, S.: The Quest for Efficient Boolean Satisfiability Solvers. In: Brinksma, E., Larsen, K.G. (eds.) CAV 2002. LNCS, vol. 2404, pp. 17–36. Springer, Heidelberg (2002)

    Chapter  Google Scholar 

  10. Prasad, M., Biere, A., Gupta, A.: A survey of recent advances in SAT-based formal verification. Software Tools for Technology Transfer 7(2), 156–173 (2005)

    Article  Google Scholar 

  11. Lu, F., Wang, L.-C., Cheng, K.-T., Moondanos, J., Hanna, Z.: A signal correlation guided ATPG solver and its applications for solving difficult industrial cases. In: Proceedings of the Design Automation Conference, pp. 436–441 (2003)

    Google Scholar 

  12. Biere, A., Cimatti, A., Clarke, E., Zhu, Y.: Symbolic Model Checking without BDDs. In: Cleaveland, W.R. (ed.) TACAS 1999. LNCS, vol. 1579, p. 193. Springer, Heidelberg (1999)

    Chapter  Google Scholar 

  13. Gupta, A., Ganai, M., Wang, C., Yang, Z., Ashar, P.: Learning from BDDs in SAT-based bounded model checking. In: Design Automation Conference (2003)

    Google Scholar 

  14. Ganai, M.K., Gupta, A., Yang, Z.-J., Ashar, P.: Efficient distributed SAT and SAT-based distributed bounded model checking. In: Geist, D., Tronci, E. (eds.) CHARME 2003. LNCS, vol. 2860, pp. 334–347. Springer, Heidelberg (2003)

    Chapter  Google Scholar 

  15. Ganai, M., Gupta, A., Ashar, P.: Beyond safety: Customized SAT-based model checking. In: Proceedings of the Design Automation Conference, pp. 738–743 (2005)

    Google Scholar 

  16. Sheeran, M., Singh, S., Stålmarck, G.: Checking safety properties using induction and a SAT-solver. In: Johnson, S.D., Hunt Jr., W.A. (eds.) FMCAD 2000. LNCS, vol. 1954, pp. 108–125. Springer, Heidelberg (2000)

    Chapter  Google Scholar 

  17. Gupta, A., Ganai, M.K., Wang, C., Yang, Z.-J., Ashar, P.: Abstraction and BDDs complement SAT-based BMC in diVer. In: Hunt Jr., W.A., Somenzi, F. (eds.) CAV 2003. LNCS, vol. 2725, pp. 206–209. Springer, Heidelberg (2003)

    Chapter  Google Scholar 

  18. Gupta, A., Yang, Z.-J., Ashar, P., Gupta, A.: SAT-based image computation with application in reachability analysis. In: Johnson, S.D., Hunt Jr., W.A. (eds.) FMCAD 2000. LNCS, vol. 1954, pp. 354–371. Springer, Heidelberg (2000)

    Chapter  Google Scholar 

  19. Gupta, A., Yang, Z., Ashar, P.: Dynamic detection and removal of inactive clauses in SAT with application in image computation. In: Proceedings of Design Automation Conference (2001)

    Google Scholar 

  20. Gupta, A., Yang, Z., Ashar, P., Zhang, L., Malik, S.: Partition-Based Decision Heuristics for Image Computation using SAT and BDDs. In: Proceedings of International Conference on Computer-Aided Design (2001)

    Google Scholar 

  21. Ganai, M., Gupta, A., Ashar, P.: Efficient SAT-based unbounded symbolic model checking using circuit cofactoring. In: Proceedings of the International Conference on Computer-Aided Design, pp. 510–517 (2004)

    Google Scholar 

  22. Gupta, A., Ganai, M., Yang, J., Ashar, P.: Iterative Abstraction using SAT-based BMC with Proof Analysis. In: Proceedings of International Conference on Computer Aided Design (ICCAD) (2003)

    Google Scholar 

  23. Gupta, A., Ganai, M., Ashar, P.: Lazy constraints and SAT heuristics for proof-based abstraction. In: Proceedings of the International Conference on VLSI Design, pp. 183–188 (2005)

    Google Scholar 

  24. Ganai, M., Kuehlmann, A.: On-the-fly compression of logical circuits. In: Proceedings of International Workshop on Logic Synthesis (2000)

    Google Scholar 

  25. Ganai, M., Zhang, L., Ashar, P., Gupta, A.: Combining Strengths of Circuit-based and CNF-based Algorithms for a High Performance SAT Solver. In: Proceedings of the Design Automation Conference (2002)

    Google Scholar 

  26. Abramovici, M., Breuer, M.A., Friedman, A.D.: Digital Systems Testing and Testable Design. Computer Science Press, Rockville (1990)

    Google Scholar 

  27. Ganai, M.K., Gupta, A., Ashar, P.: Efficient modeling of embedded memories in bounded model checking. In: Alur, R., Peled, D.A. (eds.) CAV 2004. LNCS, vol. 3114, pp. 440–452. Springer, Heidelberg (2004)

    Chapter  Google Scholar 

  28. Ganai, M., Gupta, A., Ashar, P.: Verification of embedded memory systems using efficient memory modeling. In: Proceedings of Design Automation and Test Europe (DATE), pp. 1096–1101 (2005)

    Google Scholar 

  29. Ganai, M., Gupta, A., Ashar, P.: DiVer: SAT-based model checking platform for verifying large scale systems. In: Proceedings of Tools and Algorithms for the Construction and Analysis of Systems (TACAS), pp. 575–580. Springer, Heidelberg (2005)

    Chapter  Google Scholar 

  30. Wakabayashi, K.: Cyber: High level synthesis system from software into ASIC. In: Camposano, R., Wolf, W. (eds.) High Level VLSI Synthesis, pp. 127–151. Kluwer Academic Publishers, Dordrecht (1991)

    Chapter  Google Scholar 

  31. Ivančić, F., Yang, Z., Ganai, M.K., Gupta, A., Shlyakhter, I., Ashar, P.: F-Soft: Software Verification Platform. In: Etessami, K., Rajamani, S.K. (eds.) CAV 2005. LNCS, vol. 3576, pp. 301–306. Springer, Heidelberg (2005)

    Chapter  Google Scholar 

  32. Ivancic, F., Shlyakhter, I., Gupta, A., Ganai, M., Kahlon, V., Wang, C., Yang, Z.: Model checking C programs using F-Soft. In: Proceedings of the International Conference on Computer Design, pp. 297–308 (2005)

    Google Scholar 

  33. Barrett, C.W., Dill, D.L., Stump, A.: Checking satisfiability of first-order formulas by incremental translation to SAT. In: Brinksma, E., Larsen, K.G. (eds.) CAV 2002. LNCS, vol. 2404, pp. 236–249. Springer, Heidelberg (2002)

    Chapter  Google Scholar 

  34. Seshia, S., Lahiri, S., Bryant, R.E.: A hybrid SAT-based decision procedure for separation logic with uninterpreted functions. In: Design Automation Conference (2003)

    Google Scholar 

  35. Wang, C., Ivančić, F., Ganai, M.K., Gupta, A.: Deciding separation logic formulae by SAT and incremental negative cycle elimination. In: Sutcliffe, G., Voronkov, A. (eds.) LPAR 2005. LNCS, vol. 3835, pp. 322–336. Springer, Heidelberg (2005)

    Chapter  Google Scholar 

  36. Ganai, M., Talupur, M., Gupta, A.: SDSAT: Tight integration of small domain encoding and lazy approaches in a separation logic solver. In: Proceedings of Tools and Algorithms for the Construction and Analysis of Systems (2006)

    Google Scholar 

  37. Garey, M.R., Johnson, D.S.: Computers and Intractability: A guide to the theory of NP-Completeness. W.H. Freeman and Co., New York (1979)

    MATH  Google Scholar 

  38. Larrabee, T.: Test pattern generation using Boolean Satisfiability. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 11(1), 4–15 (1992)

    Article  Google Scholar 

  39. Davis, M., Longeman, G., Loveland, D.: A Machine Program for Theorem Proving. Communications of the ACM 5, 394–397 (1962)

    Article  MathSciNet  MATH  Google Scholar 

  40. Zhang, L., Malik, S.: Validating SAT Solvers Using an Independent Resolution-Based Checker: Practical Implementations and Other Applications. In: Proceedings of Conference on Design Automation & Test Europe (DATE) (2003)

    Google Scholar 

  41. Goldberg, E., Novikov, Y.: Verification of Proofs of Unsatisfiability for CNF Formulas. In: Proceedings of Conference on Design Automation & Test Europe (DATE) (2003)

    Google Scholar 

  42. McMillan, K.L., Amla, N.: Automatic Abstraction without Counterexamples. In: Garavel, H., Hatcliff, J. (eds.) TACAS 2003. LNCS, vol. 2619, pp. 2–17. Springer, Heidelberg (2003)

    Chapter  Google Scholar 

  43. Fujiwara, H., Shimono, T.: On the Acceleration of Test Generation Algorithms. IEEE Transactions on Computers C-32(12), 265–272 (1983)

    Article  Google Scholar 

  44. Goel, P.: An implicit enumeration algorithm to generate tests for Combinational circuits. IEEE Transactions on Computers C-30(3), 215–222 (1981)

    Article  MATH  Google Scholar 

  45. Kuehlmann, A., Ganai, M., Paruthi, V.: Circuit-based Boolean Reasoning. In: Proceedings of Design Automation Conference (2001)

    Google Scholar 

  46. Kuehlmann, A., Paruthi, V., Krohm, F., Ganai, M.: Robust Boolean Reasoning for Equivalence Checking and Functional Property Verification. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 21(12), 1377–1394 (2002)

    Article  Google Scholar 

  47. Iyer, M., Parthasarthy, G., Cheng, K.-T.: SATORI – A fast sequential SAT engine for circuits. In: Proceedings of the International Conference on Computer-Aided Design, pp. 320–325 (2003)

    Google Scholar 

  48. Jin, H., Awedh, M., Somenzi, F.: CirCUs: A satisfiability solver geared towards bounded model checking. In: Alur, R., Peled, D.A. (eds.) CAV 2004. LNCS, vol. 3114, pp. 519–522. Springer, Heidelberg (2004)

    Chapter  Google Scholar 

  49. Holzmann, G.J.: The Model Checker SPIN. IEEE Transactions of Software Engineering 23(5), 279–295 (1997)

    Article  Google Scholar 

  50. Kröning, D., Strichman, O.: Efficient Computation of Recurrence Diameters. In: Zuck, L.D., Attie, P.C., Cortesi, A., Mukhopadhyay, S. (eds.) VMCAI 2003. LNCS, vol. 2575, pp. 298–309. Springer, Heidelberg (2002)

    Chapter  Google Scholar 

  51. Shtrichman, O.: Tuning SAT Checkers for Bounded Model Checking. In: Proceedings of International Conference on Computer-Aided Verification (2000)

    Google Scholar 

  52. Shtrichman, O.: Pruning Techniques for the SAT-based bounded model checking. In: Proceedings of Workshop on Tools and Algorithms for the Analysis and Construction of Systems (TACAS) (2001)

    Google Scholar 

  53. Een, N., Sorensson, N.: Temporal induction by incremental SAT solving. In: Proceedings of the First International Workshop on Bounded Model Checking (BMC). Elsevier, Amsterdam (2003)

    Google Scholar 

  54. Baumgartner, J., Kuehlmann, A., Abraham, J.A.: Property Checking via Structural Analysis. In: Brinksma, E., Larsen, K.G. (eds.) CAV 2002. LNCS, vol. 2404, p. 151. Springer, Heidelberg (2002)

    Chapter  Google Scholar 

  55. Mneimneh, M., Sakallah, K.: SAT-based sequential depth computation. In: Proceedings of the First International Workshop on Constraints in Formal Verification (2002)

    Google Scholar 

  56. Kuehlmann, A., Krohm, F.: Equivalence Checking using Cuts and Heaps. In: Proceedings of Design Automation Conference (1997)

    Google Scholar 

  57. Whittemore, J., Kim, J., Sakallah, K.: SATIRE: A new incremental SAT engine. In: Proceedings of the Design Automation Conference (2001)

    Google Scholar 

  58. Ganai, M., Aziz, A.: Improved SAT-based Bounded Reachability Analysis. In: Proceedings of VLSI Design Conference (2002)

    Google Scholar 

  59. Brayton, R., Somenzi, F., et al.: VIS: Verification Interacting with Synthesis (2002), http://vlsi.colorado.edu/~vis

  60. Cabodi, S.N., Quer, S.: Improving SAT-based bounded model checking by means of BDD-based approximate traversals. In: Proceedings of Design Automation and Test Europe, pp. 898–903 (2003)

    Google Scholar 

  61. Kurshan, R.P.: Computer-Aided Verification of Co-ordinating Processes: The Automata-Theoretic Approach. Princeton University Press, Princeton (1994)

    Google Scholar 

  62. Zhao, Y.: Accelerating Boolean Satisfiability through Application Specific Processing. In: Electrical Engineering, Princeton University, Princeton (2001)

    Google Scholar 

  63. Burch, J.R., Dill, D.: Automatic verification of pipelined microprocessor control. In: Proceedings of the International Conference on Computer Aided Verification (1994)

    Google Scholar 

  64. Bryant, R.E., German, S., Velev, M.N.: Processor verification using efficient reductions of the logic of uninterpreted functions to propositional logic. In: Proceedings of the International Conference on Computer Aided Verification (1999)

    Google Scholar 

  65. Velev, M.N.: Automatic abstraction of memories in the formal verification of superscalar microprocessors. In: Margaria, T., Yi, W. (eds.) TACAS 2001. LNCS, vol. 2031, p. 252. Springer, Heidelberg (2001)

    Chapter  Google Scholar 

  66. Bryant, R.E., Lahiri, S., Seshia, S.: Modeling and Verifying Systems using a Logic of Counter Arithmetic with Lambda Expressions and Uninterpreted Functions. In: Proceedings of Conference on Computer Aided Verification (2002)

    Google Scholar 

  67. Bjesse, P., Claessen, K.: SAT-based verification without state space traversal. In: Johnson, S.D., Hunt Jr., W.A. (eds.) FMCAD 2000. LNCS, vol. 1954, pp. 372–389. Springer, Heidelberg (2000)

    Chapter  Google Scholar 

  68. Clarke, E.M., Grumberg, O., Jha, S., Lu, Y., Veith, H.: Counterexample-guided abstraction refinement. In: Proceedings of Conference on Computer Aided Verification, pp. 154–169 (2000)

    Google Scholar 

  69. Chauhan, P., Clarke, E.M., Kukula, J., Sapra, S., Veith, H., Wang, D.: Automated Abstraction Refinement for Model Checking Large State Spaces using SAT based Conflict Analysis. In: Proceedings of Conference on Formal Methods in CAD (FMCAD) (2002)

    Google Scholar 

  70. McMillan, K.L.: Interpolation and SAT-based Model Checking. In: Proceedings of Conference on Computer-Aided Verification (2003)

    Google Scholar 

  71. Abdulla, P.A., Bjesse, P., Eén, N.: Symbolic Reachability Analysis Based on SAT-Solvers. In: Schwartzbach, M.I., Graf, S. (eds.) TACAS 2000. LNCS, vol. 1785, p. 411. Springer, Heidelberg (2000)

    Chapter  Google Scholar 

  72. Williams, P., Biere, A., Clarke, E.M., Gupta, A.: Combining Decision Diagrams and SAT Procedures for Efficient Symbolic Model Checking. In: Proceedings of International Conference on Computer-Aided Verification, pp. 124–138 (2000)

    Google Scholar 

  73. McMillan, K.L.: Applying SAT methods in unbounded symbolic model checking. In: Brinksma, E., Larsen, K.G. (eds.) CAV 2002. LNCS, vol. 2404, p. 250. Springer, Heidelberg (2002)

    Chapter  Google Scholar 

  74. Kang, H.-J., Park, I.-C.: SAT-based unbounded symbolic model checking. In: Proceedings of the Design Automation Conference (2003)

    Google Scholar 

  75. Tang, D., Malik, S., Gupta, A., Ip, N.: Symmetry reduction in SAT-based model checking. In: Proceedings of the International Conference on Computer Aided Verification, pp. 125–138 (2005)

    Google Scholar 

  76. VIS Home page, http://www-cad.eecs.berkeley.edu/~vis

  77. Gupta, A., Bayazit, A.A., Mahajan, Y.: Verification Languages. In: The Industrial Information Technology Handbook. CRC Press, Boca Raton (2005)

    Google Scholar 

  78. Williams, S.: Icarus Verilog, http://www.icarus.com/eda/verilog

Download references

Author information

Authors and Affiliations

  1. NEC Laboratories America, Princeton, USA

    Aarti Gupta, Malay K. Ganai & Chao Wang

Authors
  1. Aarti Gupta
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Malay K. Ganai
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Chao Wang
    View author publications

    You can also search for this author in PubMed Google Scholar

Editor information

Editors and Affiliations

  1. Istituto di Scienze e Tecnologie dell’Informazione, Università di Urbino “Carlo Bo”, Italy

    Marco Bernardo

  2. FBK-IRST, Povo, Trento, Italy

    Alessandro Cimatti

Rights and permissions

Reprints and permissions

Copyright information

© 2006 Springer-Verlag Berlin Heidelberg

About this paper

Cite this paper

Gupta, A., Ganai, M.K., Wang, C. (2006). SAT-Based Verification Methods and Applications in Hardware Verification. In: Bernardo, M., Cimatti, A. (eds) Formal Methods for Hardware Verification. SFM 2006. Lecture Notes in Computer Science, vol 3965. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11757283_5

Download citation

  • DOI: https://doi.org/10.1007/11757283_5

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-34304-2

  • Online ISBN: 978-3-540-34305-9

  • eBook Packages: Computer ScienceComputer Science (R0)

Publish with us

Policies and ethics

Search

Navigation