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Power Estimation of CMOS Circuits by Neural Network Macromodel

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Advances in Neural Networks - ISNN 2006 (ISNN 2006)

Part of the book series: Lecture Notes in Computer Science ((LNTCS,volume 3973))

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Abstract

Neural network is employed to construct the power macromodel of complementary metal-oxide-semiconductor (CMOS) integrated circuits. In contrast to previous modeling approaches, it does not require empirically constructed specialized analytical equations for the power macromodel, and obtained statistics of a circuit’s primary outputs simultaneously. It is suitable for power estimation in core-based systems-on-chips (SoCs) with pre-designed blocks. In experiments with the ISCAS-85 circuits, the average absolute relative error of the macromodel was below 5.0% for not only the average power dissipation, but also the maximum power dissipation.

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© 2006 Springer-Verlag Berlin Heidelberg

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Qiang, W., Cao, Y., Yan, Yy., Gao, X. (2006). Power Estimation of CMOS Circuits by Neural Network Macromodel. In: Wang, J., Yi, Z., Zurada, J.M., Lu, BL., Yin, H. (eds) Advances in Neural Networks - ISNN 2006. ISNN 2006. Lecture Notes in Computer Science, vol 3973. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11760191_191

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  • DOI: https://doi.org/10.1007/11760191_191

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-34482-7

  • Online ISBN: 978-3-540-34483-4

  • eBook Packages: Computer ScienceComputer Science (R0)

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