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A Heuristic Load Balancing Scheduling Method for Dedicated Machine Constraint

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Advances in Applied Artificial Intelligence (IEA/AIE 2006)

Abstract

The dedicated machine constraint for the photolithography process in semiconductor manufacturing is one of the new challenges introduced in photolithography machinery due to natural bias. With this constraint, the wafers passing through each photolithography process have to be processed on the same machine. The purpose of the limitation is to prevent the impact of natural bias. However, many scheduling policies or modeling methods proposed by previous research for the semiconductor manufacturing system have not discussed the dedicated machine constraint. We propose the Load Balancing (LB) scheduling method based on a Resource Schedule and Execution Matrix (RSEM) to tackle this constraint. The LB method uses the RSEM as a tool to represent the temporal relationship between the wafer lots and machines. The LB method is to schedule each wafer lot at the first photolithography stage to a suitable machine according to the load balancing factors among photolithography machines. In the paper, we present an example to demonstrate the LB method and the result of the simulations to validate our method.

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References

  1. Akcalt, E., Nemoto, K., Uzsoy, R.: Cycle-time improvements for photolithography process in semiconductor manufacturing. IEEE Transactions on Semiconductor Manufacturing 14(1), 48–56 (2001)

    Article  Google Scholar 

  2. Kumar, P.R.: Re-entrant Lines. Queuing Systems: Theory and Applications, Special Issue on Queuing Networks 13(1-3), 87–110 (1993)

    Article  MATH  Google Scholar 

  3. Kumar, P.R.: Scheduling Manufacturing Systems of Re-Entrant Lines. In: Yao, D.D. (ed.) Stochastic Modeling and Analysis of Manufacturing Systems, pp. 325–360. Springer, New York (1994)

    Chapter  Google Scholar 

  4. Lu, S.C.H., Ramaswamy, D., Kumar, P.R.: Efficient Scheduling Policies to Reduce Mean and Variance of Cycle-time in Semiconductor Manufacturing Plants. IEEE Transactions on Semiconductor Manufacturing 7(3), 374–385 (1994)

    Article  Google Scholar 

  5. Wein, L.M.: Scheduling Semiconductor Wafer Fabrication. IEEE Transactions on Semiconductor Manufacturing 1(3), 115–130 (1988)

    Article  MathSciNet  Google Scholar 

  6. Chern, C., Liu, Y.: Family-Based Scheduling Rules of a Sequence-Dependent Wafer Fabrication System. IEEE Transactions on Semiconductor Manufacturing 16(1), 15–25 (2003)

    Article  Google Scholar 

  7. Shen, Y., Leachman, R.C.: Stochastic Wafer Fabrication Scheduling. IEEE Transactions on Semiconductor Manufacturing 16(1), 2–14 (2003)

    Article  Google Scholar 

  8. Zhou, M., Jeng, M.D.: Modeling, Analysis, Simulation, Scheduling, and Control of Semiconductor Manufacturing System: A Petri Net Approach. IEEE Transactions on Semiconductor Manufacturing 11(3), 333–357 (1998)

    Article  Google Scholar 

  9. Miwa, T., Nishihara, N., Yamamoto, K.: Automated Stepper Load Balance Allocation System. IEEE Transactions on Semiconductor Manufacturing 18(4), 510–516 (2005)

    Article  Google Scholar 

  10. Arisha, A., Young, P.: Intelligent Simulation-based Lot Scheduling of Photolithography Toolsets in a Wafer Fabrication Facility. In: Winter Simulation Conference, pp. 1935–1942 (2004)

    Google Scholar 

  11. Mönch, L., Prause, M., Schmalfuss, V.: Simulation-Based Solution of Load-Balancing Problems in the Photolithography Area of a Semiconductor Wafer Fabrication Facility. In: Winter Simulation Conference, pp. 1170–1177 (2001)

    Google Scholar 

  12. Kumar, S., Kumar, P.R.: Queuing Network Models in the Design and Analysis of Semiconductor Wafer Fabs. IEEE Transactions on Robotics and Automation 17(5), 548–561 (2001)

    Article  Google Scholar 

  13. Lu, S.H., Kumar, P.R.: Distributed Scheduling Based on Due Dates and Buffer Priorities. IEEE Transactions on Automatic Control, 1406–1416 (1991)

    Google Scholar 

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© 2006 Springer-Verlag Berlin Heidelberg

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Shr, A.M.D., Liu, A., Chen, P.P. (2006). A Heuristic Load Balancing Scheduling Method for Dedicated Machine Constraint. In: Ali, M., Dapoigny, R. (eds) Advances in Applied Artificial Intelligence. IEA/AIE 2006. Lecture Notes in Computer Science(), vol 4031. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11779568_81

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  • DOI: https://doi.org/10.1007/11779568_81

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-35453-6

  • Online ISBN: 978-3-540-35454-3

  • eBook Packages: Computer ScienceComputer Science (R0)

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