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Handel-C Design Enhancement for FPGA-Based DV Decoder

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Reconfigurable Computing: Architectures and Applications (ARC 2006)

Part of the book series: Lecture Notes in Computer Science ((LNTCS,volume 3985))

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Abstract

In the paper the authors present an implementation of the algorithm of DV Decoder conformant to IEC-61834-2 standard in reprogrammable resources . A software implementation has been realized and then transferred to the Handel-C language. By parallelization of the algorithm and using language mechanisms in Handel-C the processing efficiency has been increased 10 times with respect to the initial hardware implementation. The implementation has been verified in hardware-software environment with real data transmitted on-line from a DV camcorder.

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References

  1. IEC 61834-2 (1998-08) Recording - Helical-scan digital video cassette recording system using 6.3 mm magnetic tape for consumer use (525-60, 62550, 1125-60 and 1250-50 systems), IEC (1998)

    Google Scholar 

  2. IEEE Std. 1394-1995 IEEE Standard for a High Performance Serial Bus. IEEE (1995)

    Google Scholar 

  3. Dhir, A.: IEEE 1394 and HAVi Are the Leading Technologies for Wired Home Networking. Xcell Journal 43, 48–51 (2002)

    Google Scholar 

  4. Divio and Xilinx Collaborate to deliver next-generation DV codec and decoder reference design, On-line: http://www.xilinx.com/prs_rls/design_win/01130divio.htm

  5. Merlin 2003 DV and MPEG-2 recorder and Dual Stream Decoder, Users Manual, Skymicro Inc. (2003), On-line: http://www.skymicro.com/filesm2k3/MerlinUser.pdf

  6. Richardson, I.E.G.: Video Codec Design, 1st edn. John Wiley & Sons, Chichester (2002)

    Book  Google Scholar 

  7. Loeffler, C., Ligtenberg, A., Moschytz, G.S.: Practical Fast 1-DCT Algorithms with 11 Multiplications. In: Proc. of the International Conference on Acoustics, Speech, and Signal Processing, pp. 988–991. IEEE, Los Alamitos (1989)

    Chapter  Google Scholar 

  8. van Eijndhoven, J., Sijstermans, F.: Data Processing Device and method of Computing the Cosine Transform of a Matrix. PCT Patent No, WO 9948025 (1999)

    Google Scholar 

  9. Nikara, J., Vassiliadis, S., Takala, J., Sima, M., Liuha, P.: Parallel Multiple-Symbol Variable-Length Decoding. In: Proceedings of ICCD - VLSI in Computers and Processors, pp. 126–131. IEEE, Los Alamitos (2002)

    Google Scholar 

  10. Wiatr, K., Jamro, E.: Implementation of Multipliers in FPGA Structures. In: Proc. of IEEE International Symposium on Quality Electronic Design, pp. 415–420. IEEE Computer Society, Los Alamitos (2001)

    Google Scholar 

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Author information

Authors and Affiliations

  1. Biocybernetic Laboratory, Department of Automatics, AGH University of Science and Technology, Al.Mickiewicza 30, 30-059, Kraków, Poland

    Sławomir Cichoń, Marek Gorgoń & Mirosław Pac

Authors
  1. Sławomir Cichoń
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  2. Marek Gorgoń
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  3. Mirosław Pac
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Editor information

Editors and Affiliations

  1. TU Delft, Computer Engineering Laboratory, EEMCS, The Netherlands

    Koen Bertels

  2. IST/INESC-ID, Lisboa, Portugal

    João M. P. Cardoso

  3. TUDelft., Computer Engineering Lab, Postbus 5031, 2600 GA, Delft, The Netherlands

    Stamatis Vassiliadis

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© 2006 Springer-Verlag Berlin Heidelberg

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Cichoń, S., Gorgoń, M., Pac, M. (2006). Handel-C Design Enhancement for FPGA-Based DV Decoder. In: Bertels, K., Cardoso, J.M.P., Vassiliadis, S. (eds) Reconfigurable Computing: Architectures and Applications. ARC 2006. Lecture Notes in Computer Science, vol 3985. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11802839_18

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  • DOI: https://doi.org/10.1007/11802839_18

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-36708-6

  • Online ISBN: 978-3-540-36863-2

  • eBook Packages: Computer ScienceComputer Science (R0)

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