Abstract
In the paper the authors present an implementation of the algorithm of DV Decoder conformant to IEC-61834-2 standard in reprogrammable resources . A software implementation has been realized and then transferred to the Handel-C language. By parallelization of the algorithm and using language mechanisms in Handel-C the processing efficiency has been increased 10 times with respect to the initial hardware implementation. The implementation has been verified in hardware-software environment with real data transmitted on-line from a DV camcorder.
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References
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© 2006 Springer-Verlag Berlin Heidelberg
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Cichoń, S., Gorgoń, M., Pac, M. (2006). Handel-C Design Enhancement for FPGA-Based DV Decoder. In: Bertels, K., Cardoso, J.M.P., Vassiliadis, S. (eds) Reconfigurable Computing: Architectures and Applications. ARC 2006. Lecture Notes in Computer Science, vol 3985. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11802839_18
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DOI: https://doi.org/10.1007/11802839_18
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-36708-6
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