Abstract
We propose the multiple LUT cascade as a means to configure an n-input LPM (Longest Prefix Match) address generator commonly used in routers to determine the output port given an address. The LPM address generator accepts n-bit addresses which it matches against k stored prefixes. We implement our design on a Xilinx Spartan-3 FPGA for n = 32 and k = 504 ~511. Also, we compare our design to a Xilinx proprietary TCAM (ternary content-addressable memory) design and to another design we propose as a likely solution to this problem. Our best multiple LUT cascade implementation has 5.20 times more throughput, 31.71 times more throughput/area and is 2.89 times more efficient in terms of area-delay product than Xilinx’s proprietary design. Furthermore, its area is only 19% of Xilinx’s design.
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Qin, H., Sasao, T., Butler, J.T. (2006). Implementation of LPM Address Generators on FPGAs. In: Bertels, K., Cardoso, J.M.P., Vassiliadis, S. (eds) Reconfigurable Computing: Architectures and Applications. ARC 2006. Lecture Notes in Computer Science, vol 3985. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11802839_24
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DOI: https://doi.org/10.1007/11802839_24
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