Abstract
The design of electronic systems in a System-on-Chip (SoC) depends on the reliable and efficient interconnection of many different components. The Network-on-Chip (NoC) has emerged as a scalable communication infrastructure with high bandwidth able to tackle the communication needs of future SoC. In this paper, we present a generic NoC architecture that can be customized to the specific communication needs of an application in order to reduce the area with minimal degradation of the latency of the system.
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Guerrier, P., Greiner, A.: A generic architecture for on-chip packet-switched interconnections. In: DATE (2000)
Hemani, A., et al.: Network on chip: An arquitectura for billion transistor era. In: Proceedings of the IEEE NorChip Conference (2000)
Dally, W., Towles, B.: Route packets, not wires: on-chip interconnection networks. In: Proceedings of DAC (2001)
Murali, S., Micheli, G.: Bandwidth-constrained mapping of cores onto NoC architetcures. In: DATE (2004)
Lei, T., Kumar, S.: A two-step genetic algorithm for mapping task graphs to a NoC architecture. In: DSD (2003)
Kreutz, M., et al.: Design space exploration comparing homogeneous and heterogeneous network-on-chip architectures. SBCCI (2005)
Benini, L., Micheli, G.: Networks on chips: a new SoC paradigm. SBCCI Computer 35(1), 70–78 (2005)
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© 2006 Springer-Verlag Berlin Heidelberg
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Véstias, M.P., Neto, H.C. (2006). Area/Performance Improvement of NoC Architectures. In: Bertels, K., Cardoso, J.M.P., Vassiliadis, S. (eds) Reconfigurable Computing: Architectures and Applications. ARC 2006. Lecture Notes in Computer Science, vol 3985. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11802839_27
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DOI: https://doi.org/10.1007/11802839_27
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-36708-6
Online ISBN: 978-3-540-36863-2
eBook Packages: Computer ScienceComputer Science (R0)