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The Emergence of Non-von Neumann Processors

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Reconfigurable Computing: Architectures and Applications (ARC 2006)

Part of the book series: Lecture Notes in Computer Science ((LNTCS,volume 3985))

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Abstract

The von Neumann processor has been the foundation of computing from the start. Today’s instruction processors are powerful and scale to thousands to yield large compute power, but a small fraction of the peak. The ASIC chip technology that implementations the fixed design microprocessor is placing significant constraints on the design of processors. At the same time reconfigurable Processors based upon FPGA chip technology are growing in capability and performance using a nontraditional processor architecture without instructions (the non-von Neumann architecture). Both processor types are trending to a common design point. This paper explores these trends and explains the technology of the emerging non-von Neumann processor and presents an example implementation.

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Author information

Authors and Affiliations

  1. SRC Computers, Inc., Colorado Springs, CO, USA

    Daniel S. Poznanovic

Authors
  1. Daniel S. Poznanovic
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Editor information

Editors and Affiliations

  1. TU Delft, Computer Engineering Laboratory, EEMCS, The Netherlands

    Koen Bertels

  2. IST/INESC-ID, Lisboa, Portugal

    João M. P. Cardoso

  3. TUDelft., Computer Engineering Lab, Postbus 5031, 2600 GA, Delft, The Netherlands

    Stamatis Vassiliadis

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© 2006 Springer-Verlag Berlin Heidelberg

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Poznanovic, D.S. (2006). The Emergence of Non-von Neumann Processors. In: Bertels, K., Cardoso, J.M.P., Vassiliadis, S. (eds) Reconfigurable Computing: Architectures and Applications. ARC 2006. Lecture Notes in Computer Science, vol 3985. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11802839_32

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  • DOI: https://doi.org/10.1007/11802839_32

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-36708-6

  • Online ISBN: 978-3-540-36863-2

  • eBook Packages: Computer ScienceComputer Science (R0)

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