Abstract
The emergence of the Network on chip (NoC) as a communication backbone for System on chip (SoC) based designs requires standardized interfaces for integrating IP (Intellectual Property) cores with diverse communication requirements. These interfaces have to be simple and generic for rapid plug and play implementation with minimal overhead. In this paper we describe the design and implementation of a programmable fabric based Network interface architecture. We have mapped the JPEG compression application on our architecture to demonstrate the feasibility of our design. The network interfaces seamlessly connect existing IP modules (Processor core, JPEG core, Memory core and UART core) to the NoC. The network, IP cores and the network interfaces are implemented on an FPGA device.
Preview
Unable to display preview. Download preview PDF.
Similar content being viewed by others
References
De Micheli, G., Benini, L.: Networks on chips: A new soc paradigm. IEEE Computer 35(1) (2002)
B.P.M.R.: Interfacing cores with on-chip packet-switched networks. In: Proceedings of the 16th International Conference on VLSI Design, pp. 382 – 387 (January 2003)
Adriahantenaina, A., Charlery, H., Greiner, A., Mortiez, L., Zeferino, C.A.: Spin: a scalable, packet switched, on-chip micronetwork. In: Proc. IEEE Design Automation and Test (2003)
Zeferino, C., Susin, A.: Socin: a parametric and scalable network-on-chip. In: Proc. 16th Symposium on Integrated Circuits and Systems Design (September 2003)
Zeferino, C., Kreutz, M., Susin, A.A.: Rasoc: a router soft-core for networks-on-chip. In: Proc. Design, Automation and Test in Europe Conference and Exhibition, vol. 3, pp. 198–203 (February 2001)
Gurrier, P., Greiner, A.: A generic architecture for on-chip packet switched interconnections. In: Proc. IEEE Design Automation and Test (March 2000)
Holsmark, R., Johansson, A., Kumar, S.: On connecting cores to packet switched on-chip networks: A case study with microblaze processor cores. In: IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (April 2004)
Dielissen, J., Radulescu, A., Goossens, K., Rijpkema, E.: Concepts and implementation of the philips network-on-chip. In: IP-SOC Workshop (November 2003)
Ni, L.M., McKinley, P.K.: A survey of wormhole routing techniques in direct networks. IEEE Transaction on Computers, 62–76 (February 1993)
Wallace, G.K.: The jpeg still picture compression standard. IEEE Transactions on Comsumer Electronics 38(1), xviii–xxxiv (1992)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2006 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Singh, S.P., Bhoj, S., Balasubramanian, D., Nagda, T., Bhatia, D., Balsara, P. (2006). Generic Network Interfaces for Plug and Play NoC Based Architecture. In: Bertels, K., Cardoso, J.M.P., Vassiliadis, S. (eds) Reconfigurable Computing: Architectures and Applications. ARC 2006. Lecture Notes in Computer Science, vol 3985. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11802839_37
Download citation
DOI: https://doi.org/10.1007/11802839_37
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-36708-6
Online ISBN: 978-3-540-36863-2
eBook Packages: Computer ScienceComputer Science (R0)