Abstract
The segmented bus is a power-efficient architecture for intra-tile SoC communication, where energy is saved by switching off unused bus segments cycle-by-cycle. We determine the pattern of switch control bits and calculate the cost of transporting them. A test case indicates that the cost is much lower than the gain obtained from the segmentation, and that the prospects of segmented buses remain promising.
This is a preview of subscription content, log in via an institution to check access.
Preview
Unable to display preview. Download preview PDF.
Similar content being viewed by others
References
The ATOMIUM tool suite, http://www.imec.be/design/atomium/
Catthoor, F., et al.: Custom memory management methodology exploration of memory organization for embedded multimedia system design. Kluwer, Dordrecht (1998)
Chen, J.Y., et al.: Segmented bus design for low-power systems. IEEE VLSI (March 1999)
Duato, J., et al.: Interconnection networks, an engineering approach. IEEE Computer Society, Los Alamitos (1997)
Dutta, S., et al.: Viper: a multiprocessor SoC for advanced set-top box and digital TV systems. IEEE Design & Test (September 2001)
Gangwar, A., et al.: Evaluation of bus based interconnect mechanisms in clustered VLIW architectures. DATE (2005)
Guo, J., et al.: Physical design implementation of segmented buses to reduce communication energy. In: ASP-DAC (2006)
Khailany, B., et al.: Imagine: media processing with streams. IEEE Micro (March 2001)
Li, Y., et al.: Prefix computation using a segmented bus. In: Southeastern Symposium on System Theory (April 1996)
Blast Chip 4.0 User Guide Magma Design Automation, Cupertino, CA 95014, pp. 271–351, http://www.magma-da.com
Papanikolaou, A., et al.: Architectural and physical design optimizations for efficient intra-tile communication. In: Proc. Intnl. SoC Symp., Finland (November 2005)
TMS320VC5471 fixed-point digital signal processor data manual, http://focus.ti.com/docs/prod/folders/print/tms320vc5471.html
TMS320VC5510/5510A Fixed-Point Digital Signal Processors, http://focus.ti.com/docs/prod/folders/print/tms320vc5510.html
Van Meeuwen, T., et al.: System-level interconnect architecture exploration for custom memory organisations. In: ISSS (2001)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2006 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Heyrman, K., Papanikolaou, A., Catthoor, F., Veelaert, P., Debosschere, K., Philips, W. (2006). Energy Consumption for Transport of Control Information on a Segmented Software-Controlled Communication Architecture. In: Bertels, K., Cardoso, J.M.P., Vassiliadis, S. (eds) Reconfigurable Computing: Architectures and Applications. ARC 2006. Lecture Notes in Computer Science, vol 3985. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11802839_8
Download citation
DOI: https://doi.org/10.1007/11802839_8
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-36708-6
Online ISBN: 978-3-540-36863-2
eBook Packages: Computer ScienceComputer Science (R0)