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Catching and Identifying Bugs in Register Allocation

  • Conference paper
Static Analysis (SAS 2006)

Part of the book series: Lecture Notes in Computer Science ((LNPSE,volume 4134))

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Abstract

Although there are many register allocation algorithms that work well, it can be difficult to correctly implement these algorithms. As a result, it is common for bugs to remain in the register allocator, even after the compiler is released. The register allocator may run, but bugs can cause it to produce incorrect output code. The output program may even execute properly on some test data, but errors can remain. In this paper, we propose novel data flow analyses to statically check that the output code from the register allocator is correct in terms of its data dependences. The approach is accurate, fast, and can identify and report error locations and types. No false alarms are produced. The paper describes our approach, called SARAC, and a tool, called ra-analyzer, that statically checks a register allocation and reports the errors it finds. The tool has an average compile-time overhead of only 8% and a modest average memory overhead of 85KB.

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References

  1. Benitez, M.E., Davidson, J.W.: A portable global optimizer and linker. In: ACM SIGPLAN Conf. on Programming Language Design and Implementation (June 1988)

    Google Scholar 

  2. Bernstein, D., Goldin, D.Q., et al.: Spill code minimization techniques for optimizing compilers. In: ACM SIGPLAN Conf. on Programming Language Design and Implementation (June 1989)

    Google Scholar 

  3. Bradlee, D.G., Eggers, S.J., Henry, R.R.: Integrating register allocation and instruction scheduling for RISCs. In: 4th Int’l. Conf. on Architectural Support for Programming Languages and Operating Systems (April 1991)

    Google Scholar 

  4. Briggs, P., Cooper, K.D., Torczon, L.: Improvements to graph coloring register allocation. ACM Trans. on Programming Languages and Systems 3(16), 428–455 (1994)

    Article  Google Scholar 

  5. Briggs, P., Cooper, K.D., Torczon, L.: Rematerialization. In: ACM SIGPLAN Conf. on Programming Language Design and Implementation (June 1992)

    Google Scholar 

  6. Chaitin, G.J.: Register allocation & spilling via graph coloring. In: Symp. on Compiler Construction (June 1982)

    Google Scholar 

  7. Chow, F.C., Hennessy, J.L.: The priority-based register allocation coloring approach. ACM Trans. on Programming Languages and Systems 4(12), 501–536 (1990)

    Article  Google Scholar 

  8. CPU 2000, benchmark. Standard Performance Evaluation Corporation (SPEC) (2000), http://www.spec.org

  9. Davidson, J.W., Fraser, C.W.: Register allocation and exhaustive peephole optimization. Software — Practice and Experience 14(9), 857–865 (1984)

    Article  Google Scholar 

  10. GCC, http://gcc.gnu.org/

  11. George, L., Appel, A.W.: Iterated register coalescing. ACM Trans. on Programming Languages and Systems 3(18), 300–324 (1996)

    Article  Google Scholar 

  12. Gupta, R., Soffa, M.L., Steele, T.: Register allocation via clique separators. In: ACM SIGPLAN Conf. on Programming Language Design and Implementation (July 1989)

    Google Scholar 

  13. Jaramillo, C.S., Gupta, R., Soffa, M.L.: Verifying optimizers through comparison checking. In: Int’l. Workshop on Compiler Optimization Meets Compiler Verification (April 2002)

    Google Scholar 

  14. Lacey, D., Jones, N.D., Wyk, E.V., Frederiksen, C.C.: Proving correctness of compiler optimizations by temporal logic. In: Symp. on Principles of Programming Languages (January 2002)

    Google Scholar 

  15. Lee, C., Potkonjak, M., Mangione-Smith, W.H.: MediaBench: a tool for evaluating and synthesizing multimedia and communications systems. In: ACM/IEEE Int’l. Symp. on Microarchitecture (1997)

    Google Scholar 

  16. Lerner, S., Millstein, T., Chambers, C.: Automatically proving the correctness of compiler optimizations. In: ACM SIGPLAN Conf. on Programming Language Design and Implementation (June 2003)

    Google Scholar 

  17. Lerner, S., Millstein, T., Rice, E., Chambers, C.: Automated soundness proofs for dataflow analyses and transformations via local rules. In: Symp. on Principles of Programming Languages (2005)

    Google Scholar 

  18. McNerney, T.M.: Verifying the correctness of compiler transformations on basic blocks using abstract interpretation. In: ACM/SIGPLAN Workshop Partial Evaluation and Semantics-Based Program Manipulation (1991)

    Google Scholar 

  19. MiBench. University of Michigan, http://www.eecs.umich.edu/mibench/

  20. Naik, M., Palsberg, J.: Correctness of ILP-based register allocation. (unpublished manuscript), http://theory.stanford.edu/~mhn/pubs/regalloc.pdf

  21. Necula, G.C.: Translation validation for an optimizing compiler. In: ACM SIGPLAN Conf. on Programming Language Design and Implementation (June 2000)

    Google Scholar 

  22. Necula, G.C., Lee, P.: The design and implementation of a certifying compiler. In: ACM SIGPLAN Conf. on Programming Language Design and Implementation (June 1998)

    Google Scholar 

  23. Ohori, A.: Register allocation by proof transformation. In: Degano, P. (ed.) ESOP 2003. LNCS, vol. 2618, pp. 399–413. Springer, Heidelberg (2003)

    Chapter  Google Scholar 

  24. Pinter, S.S.: Register allocation with instruction scheduling: a new approach. In: ACM SIGPLAN Conf. on Programming Language Design and Implementation (June 1993)

    Google Scholar 

  25. Pnueli, A., Siegel, M.D., Singerman, E.: Translation validation. In: Steffen, B. (ed.) TACAS 1998. LNCS, vol. 1384, p. 151. Springer, Heidelberg (1998)

    Chapter  Google Scholar 

  26. Poletto, M., Sarkar, V.: Linear scan register allocation. ACM Trans. on Programming Languages and Systems 5(21), 895–913 (1999)

    Article  Google Scholar 

  27. Rinard, M.C.: Credible compilation. Technical Report MIT-LCS-TR-776, MIT (March 1999)

    Google Scholar 

  28. Santhanam, V., Odnert, D.: Register allocation across procedure and module boundaries. In: ACM SIGPLAN Conf. on Programming Language Design and Implementation (June 1990)

    Google Scholar 

  29. Smith, M.D., Holloway, G.: Machine SUIF, http://www.eecs.harvard.edu/hube/research/machsuif.html

  30. Smith, M.D., Ramsey, N., Holloway, G.: A generalized algorithm for graph-coloring register allocation. In: ACM SIGPLAN Conf. on Programming Language Design and Implementation (June 2004)

    Google Scholar 

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Author information

Authors and Affiliations

  1. Department of Computer Science, University of Pittsburgh, Pittsburgh, Pennsylvania, 15260

    Yuqiang Huang & Bruce R. Childers

  2. Department of Computer Science, University of Virginia, Charlottesville, Virginia, 22904

    Mary Lou Soffa

Authors
  1. Yuqiang Huang
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  2. Bruce R. Childers
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  3. Mary Lou Soffa
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Editor information

Editors and Affiliations

  1. Seoul National University, P.O. Box, Korea

    Kwangkeun Yi

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© 2006 Springer-Verlag Berlin Heidelberg

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Huang, Y., Childers, B.R., Soffa, M.L. (2006). Catching and Identifying Bugs in Register Allocation. In: Yi, K. (eds) Static Analysis. SAS 2006. Lecture Notes in Computer Science, vol 4134. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11823230_19

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  • DOI: https://doi.org/10.1007/11823230_19

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-37756-6

  • Online ISBN: 978-3-540-37758-0

  • eBook Packages: Computer ScienceComputer Science (R0)

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