Abstract
This paper analyzes energy minimization of digital circuits operating at supply voltages above threshold and in the sub-threshold region. Circuit sizing and supply-voltage selection are simultaneously analyzed to determine where the minimum energy solution occurs. In this work we address the effects of architectural modifications on the design choices in different regions of operation. Two new architectural parameters are introduced that can be used for fast design comparison in the low power region of operation.
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Vratonjic, M., Zeydel, B.R., Oklobdzija, V.G. (2006). Circuit Sizing and Supply-Voltage Selection for Low-Power Digital Circuit Design. In: Vounckx, J., Azemard, N., Maurine, P. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2006. Lecture Notes in Computer Science, vol 4148. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11847083_15
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DOI: https://doi.org/10.1007/11847083_15
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-39094-7
Online ISBN: 978-3-540-39097-8
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