Abstract
In this work, we develop simple yet very effective bus encoding schemes that dramatically reduce both self and coupling transition activity in common DSP signals. We show that, efficient low-power codes must cope with the different statistical characteristics of the most and least significant bits. On one hand, the high correlation in the most significant bits can be exploited by employing a simple non-redundant code. On the other hand, Bus Invert based codes are very efficient when applied only on the poorly correlated uniformly distributed least significant bits. The latter should not be employed on the most significant bits in order to preserve their high correlation. Additionally, we show that low-power codes can be easily compared by means of a simple graphical method.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Benini, L., Macii, A., Macii, E., Poncino, M., Scarsi, R.: Architectures and Synthesis Algorithms for Power-Efficient Bus Interfaces. IEEE Trans. on Computer-Aided Design (CAD) of Integrated Circuits and Systems 19(9), 969–980 (2000)
García Ortiz, A., Murgan, T., Kabulepa, L.D., Indrusiak, L.S., Glesner, M.: High-Level Estimation of Power Consumption in Point-to-Point Interconnect Architectures. Journal of Integrated Circuits and Systems 1(1), 23–31 (2004)
International Technology Roadmap for Semiconductors, 2005 Edition. Interconnect (January 2006), http://www.itrs.net/
Landman, P.E., Rabaey, J.M.: Power Estimation for High-level Synthesis. In: European Conf. on Design Automation with the European Event in ASIC Design, Paris, France, pp. 22–25 (February 1993)
Landman, P.E., Rabaey, J.M.: Architectural Power Analysis: The Dual Bit Type Model. IEEE Trans. on Very Large Scale Integration (VLSI) Systems 3(2), 173–187 (1995)
Lyuh, C.-G., Kim, T., Kim, K.-W.: Coupling-Aware High-level Interconnect Synthesis for Low Power. In: Intl. Conf. on Computer-Aided Design (ICCAD), San Jose, California, pp. 609–613 (November 2002)
Nanoscale Integration and Modeling (NIMO) Group, Arizona State Univ. Predictive Technology Model (December 2005), http://www.eas.asu.edu/ptm/
Ramprasad, S., Shanbag, N.R., Hajj, I.N.: A Coding Framework for Low-Power Address and Data Busses. IEEE Trans. on Very Large Scale Integration (VLSI) Systems 7(2), 212–221 (1999)
Ramprasad, S., Shanbhag, N.R., Hajj, I.N.: Analytical Estimation of Signal Transition Activity from Word-Level Statistics. IEEE Trans. on Computer-Aided Design (CAD) of Integrated Circuits and Systems 16(7), 718–733 (1997)
Shin, Y., Chae, S.-I., Choi, K.: Partial Bus-Invert Coding for Power Optimization of Application-Specific Systems 9(2), 377–383 (2001)
Sotiriadis, P.P., Chandrakasan, A.P.: Low Power Coding Techniques Considering Inter-Wire Capacitance. In: Custom Integrated Circuits Conf., Orlando, Florida, pp. 507–510 (May 2000)
Stan, M.R., Burleson, W.P.: Bus-Invert Coding for Low-Power I/O. IEEE Trans. on Very Large Scale Integration (VLSI) Systems 3(1), 49–58 (1995)
Stan, M.R., Burleson, W.P.: Low-Power Encodings for Global Communication in CMOS VLSI. IEEE Trans. on Very Large Scale Integration (VLSI) Systems 5(4), 444–455 (1997)
Zhang, Y., Lach, J., Skadron, K., Stan, M.R.: Odd/Even Bus Invert with Two-Phase Transfer for Buses with Coupling. In: Intl. Symp. on Low Power Electronics and Design (ISLPED), Monterey, California, pp. 80–83 (August 2002)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2006 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Murgan, T., Bacinschi, P.B., Ortiz, A.G., Glesner, M. (2006). Partial Bus-Invert Bus Encoding Schemes for Low-Power DSP Systems Considering Inter-wire Capacitance. In: Vounckx, J., Azemard, N., Maurine, P. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2006. Lecture Notes in Computer Science, vol 4148. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11847083_17
Download citation
DOI: https://doi.org/10.1007/11847083_17
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-39094-7
Online ISBN: 978-3-540-39097-8
eBook Packages: Computer ScienceComputer Science (R0)