Abstract
Timing analysis of complex state-of-the-art designs demands efficient algorithms able to cope with design complexity. Exploring the hierarchical information generally encountered in complex designs became mandatory to perform functional timing analysis (FTA) in acceptable execution times. Although several hierarchical FTA approaches exist, only path-based hierarchical FTA is able to identify global critical paths, thus helping designers in the optimization task. In this paper we propose two versions of path-based hierarchical FTA strategies. These versions are compared to flat-mode FTA and to commercial FTA tools that operate in hierarchical mode.
This works was supported by CNPq Brazilian Agency.
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© 2006 Springer-Verlag Berlin Heidelberg
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Ferrão, D.L., Reis, R., Güntzel, J.L. (2006). Considering Zero-Arrival Time and Block-Arrival Time in Hierarchical Functional Timing Analysis. In: Vounckx, J., Azemard, N., Maurine, P. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2006. Lecture Notes in Computer Science, vol 4148. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11847083_29
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DOI: https://doi.org/10.1007/11847083_29
Publisher Name: Springer, Berlin, Heidelberg
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