Abstract
In adiabatic circuits, the energy dissipation occurs during every cycle, as output nodes are always charged and discharged by power-clocks. This paper presents a low-power register file based on adiabatic logic with power-gating techniques. N-type adiabatic drivers with power-gating schemes are used to drive read bit and read data lines, while P-type adiabatic drivers with power-gating schemes are used to drive write bit lines and power storage cells. The write and read drivers for driving bit and word lines can be switched off to reduce energy losses during idle times. The energy of all nodes with large capacitances including storage cells can be well recovered without non-adiabatic loss. SPICE simulations indicate that the proposed register file achieves considerable energy savings over CMOS implementation.
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Hu, J., Li, H., Wu, Y. (2006). Low-Power Register File Based on Adiabatic Logic Circuits. In: Vounckx, J., Azemard, N., Maurine, P. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2006. Lecture Notes in Computer Science, vol 4148. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11847083_37
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DOI: https://doi.org/10.1007/11847083_37
Publisher Name: Springer, Berlin, Heidelberg
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