Abstract
In this work, we develop two methods to improve the accuracy of memory power estimation. Our enhanced memory power model can consider not only the operation mode of memory access, but also the address switching effect and the scaling factors that use the information of physical architecture. The proposed approach is very useful to be combined with memory compiler to generate accurate power model for any specified memory size without extra characterization costs. Then the proposed dummy modular approach can link our enhanced memory power model into commercial power estimation flow smoothly. The experimental results have shown that the average error of our memory power model is only less than 5%.
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Hsieh, WT., Yu, CC., Liu, CN.J., Chiu, YF. (2006). A Scalable Power Modeling Approach for Embedded Memory Using LIB Format. In: Vounckx, J., Azemard, N., Maurine, P. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2006. Lecture Notes in Computer Science, vol 4148. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11847083_53
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DOI: https://doi.org/10.1007/11847083_53
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-39094-7
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