Abstract
In this communication, a model of the precharged bus power consumption in digital VLSI circuits is developed. This model is used to analytically evaluate the result of a multi-bit Differential Power Attack (DPA) to the address bus of cryptographic ICs running the DES algorithm. This attack to the address bus is based on the observation of its power consumption, and is well known to be a major threat to the security of the confidential information stored or processed by SmartCards. The results allow to achieve a quantitative model of the DPA attack effectiveness, and is useful as a theoretical basis to understand the trade-offs involved in DPA attacks. This deeper understanding is useful to identify the cases where a SmartCard under attack is weaker with respect to DPA attacks, i.e. when the power consumption reveals the maximum amount of information. Cycle-accurate simulations on DES encryption algorithm running on a MIPS32® architecture are used to validate the model and the underlying assumptions.
This is a preview of subscription content, log in via an institution to check access.
Preview
Unable to display preview. Download preview PDF.
Similar content being viewed by others
References
Menezes, A., Van Oorschot, P., Vanstone, S.: Handbook of Applied Cryptography. CRC Press, Boca Raton (1997)
Rankl, W., Effing, W.: SmartCard Handbook. John Wiley & Sons, Chichester (1999)
Messerges, T.S., Dabbish, E.A., Sloan, R.H.: Examining Smart-Card Security under the Threat of Power Analysis Attacks. IEEE Trans. on Computers 51(5), 541–552 (2002)
Kocher, P.C., Jaffe, J., Jun, B.: Differential Power Analysis. In: Wiener, M. (ed.) CRYPTO 1999. LNCS, vol. 1666, pp. 388–397. Springer, Heidelberg (1999)
Zhuang, X., Zhang, T., Pande, S.: HIDE: an infrastructure for efficiently protecting information leakage on the address bus. In: Proc. of ASPLOS 2004, Boston, USA, October 2004, pp. 72–84 (2004)
Messerges, T.S., Dabbish, E.A., Sloan, R.H.: Investigations of power analysis attacks on SmartCards. In: Proc. of USENIX Workshop on Smartcard Technology, Chicago, USA, pp. 388–397 (1999)
Clavier, C., Coron, J.-S., Dabbous, N.: Differential Power Analysis in the Presence of Hardware Countermeasures. In: Paar, C., Koç, Ç.K. (eds.) CHES 2000. LNCS, vol. 1965, pp. 252–263. Springer, Heidelberg (2000)
Papoulis, A.: Probability, Random Variables, and Stochastic Processes. McGraw-Hill, New York (1965)
Rabaey, J.: Digital Integrated Circuits (A Design Perspective). Prentice-Hall, Englewood Cliffs (1996)
Shannon, C.: Communication Theory of Secrecy Systems. Bell Systems Technical Journal 28, 656–715 (1949)
Lin, R.B., Tsai, C.M.: Theoretical analysis of bus-invert coding. IEEE Trans. on VLSI Systems 10(6), 929–935 (2002)
MIPS Technologies Inc., http://www.mips.com
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2006 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Alioto, M., Poli, M., Rocchi, S., Vignoli, V. (2006). Power Modeling of Precharged Address Bus and Application to Multi-bit DPA Attacks to DES Algorithm. In: Vounckx, J., Azemard, N., Maurine, P. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2006. Lecture Notes in Computer Science, vol 4148. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11847083_58
Download citation
DOI: https://doi.org/10.1007/11847083_58
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-39094-7
Online ISBN: 978-3-540-39097-8
eBook Packages: Computer ScienceComputer Science (R0)