Abstract
In this communication, different techniques to improve the resistance to Differential Power Analysis (DPA) attacks of precharged busses are discussed. These statistical attacks rely on the observation of the power consumption, and are very effective in recovering confidential information that are stored or processed in SmartCards running cryptographic algorithms. Accordingly, a few techniques to improve the information security by reducing the effectiveness of DPA attacks are discussed. These techniques are statistically analyzed and compared in terms of DPA resistance, power and area overhead. Finally, these techniques are mixed to improve the robustness to DPA attacks. Cycle-accurate simulations on DES encryption algorithm running on a MIPS32® architecture are used to validate the discussed techniques.
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Menezes, A., Van Oorschot, P., Vanstone, S.: Handbook of Applied Cryptography. CRC Press, Boca Raton (1997)
Rankl, W., Effing, W.: SmartCard Handbook. John Wiley & Sons, Chichester (1999)
Messerges, T.S., Dabbish, E.A., Sloan, R.H.: Examining Smart-Card Security under the Threat of Power Analysis Attacks. IEEE Trans. on Computers 51(5), 541–552 (2002)
Kocher, P.C.: Timing Attacks on Implementations of Diffie-Hellman, RSA, DSS, and Other Systems. In: Koblitz, N. (ed.) CRYPTO 1996. LNCS, vol. 1109, pp. 104–113. Springer, Heidelberg (1996)
Kocher, P.C., Jaffe, J., Jun, B.: Differential Power Analysis. In: Wiener, M. (ed.) CRYPTO 1999. LNCS, vol. 1666, pp. 388–397. Springer, Heidelberg (1999)
Messerges, T.S., Dabbish, E.A., Sloan, R.H.: Investigations of power analysis attacks on SmartCards. In: Proc. of USENIX Workshop on Smartcard Technology, Chicago, USA (1999)
Papoulis, A.: Probability, Random Variables, and Stochastic Processes. McGraw-Hill, New York (1965)
Rabaey, J., Chandrakasan, A., Nikolic, B.: Digital Integrated Circuits (A Design Perspective). Prentice-Hall, Englewood Cliffs (2003)
Lin, R.B., Tsai, C.M.: Theoretical analysis of bus-invert coding. IEEE Trans. on VLSI Systems 10(6), 929–935 (2002)
Stan, M.R., Burleson, W.P.: Bus-invert coding for low-power I/O. IEEE Trans. on VLSI Systems 3(1), 49–58 (1995)
Stan, M.R., Burleson, W.P.: Low-power encodings for global communication in CMOS VLSI. IEEE Trans. on VLSI Systems 5(4), 444–455 (1997)
MIPS Technologies Inc., http://www.mips.com
Federal Information Processing Standards Publication (FIPS PUB) 46-3, http://csrc.nist.gov/publications/fips/fips46-3/fips46-3.pdf
National Institute of Standards and Technology (NIST) Special Publication 800-17, http://csrc.nist.gov/publications/nistpubs/800-17/800-17.pdf
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Alioto, M., Poli, M., Rocchi, S., Vignoli, V. (2006). Techniques to Enhance the Resistance of Precharged Busses to Differential Power Analysis. In: Vounckx, J., Azemard, N., Maurine, P. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2006. Lecture Notes in Computer Science, vol 4148. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11847083_61
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DOI: https://doi.org/10.1007/11847083_61
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-39094-7
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