Abstract
Based on a first order model of the switching current flowing in CMOS cell, an investigation of the robustness against DPA of dual-rail logic is carried out. The result of this investigation, performed on 130nm process, is a formal identification of the design range in which dual-rail logic can be considered as robust.
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Razafindraibe, A., Robert, M., Maurine, P. (2006). Formal Evaluation of the Robustness of Dual-Rail Logic Against DPA Attacks. In: Vounckx, J., Azemard, N., Maurine, P. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2006. Lecture Notes in Computer Science, vol 4148. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11847083_62
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DOI: https://doi.org/10.1007/11847083_62
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