Abstract
The analysis of circuit switching activity is a fundamental step towards dynamic power estimation of CMOS digital circuits. In this paper, a probabilistic method for switching activity estimation of VHDL-RTL combinatorial designs is presented. Switching activity estimation is performed through the propagation of input signals probabilities and switching activities by means of BDDs (Binary Decision Diagrams). In order to avoid the BDD memory explosion of large circuits, an automatic circuit partition is performed taking advantage of the specific characteristics of some VHDL statements that permit the circuit division in exclusive regions. In addition, a reduced representation of switching activity BDDs is proposed. The method is implemented in a CAD tool, which, besides the signal probabilities and switching activities, offers abundant information and means for circuit exploration.
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References
International Roadmap for Semiconductors 2005 edn., http://public.itrs.net
Horowitz, M., Alon, E., Patil, D., Naffziger, S., Kumar, R.: Scaling, Power, and the Future of CMOS. In: IEEE Int. Electron Devices Meeting, Washington DC, USA (December 2005)
Bryant, R.: Graph-Based Algorithms for Boolean Function Manipulation. IEEE Trans. on Computers 35(8) (August 1986)
Nardi, A., Zeng, H., Garret, J., Daniel, L., Sangiovanni-Vicentelli, A.: A Methodology for the Computation of an Upper Bound on Noise Current Spectrum of CMOS Switching Activity. In: ICCAD, San Jose, CA, USA (November 2003)
Méndez, M., González, J., Mateo, D., Rubio, A.: An Investigation on the Relation between Digital Circuitry Characteristics and Power Supply Noise Spectrum in Mixed-Signal CMOS Integrated Circuits. Microelectronics Journal 36(1) (January 2005)
Agarwal, A., Mukhopadhyay, S., Kim, C.H., Raychowdhury, A., Roy, K.: Leakage Power Analysis and Reduction: Models, Estimation and Tools. IEE Proc. - Computers and Digital Techniques 152(3) (May 2005)
Ferré, A., Figueras, J.: On Estimating Leakage Power Consumption for Submicron CMOS Digital Circuits. In: PATMOS, Belgium (September 1997)
Soudris, D., Piguet, C., Goutis, C.: Designing CMOS circuits for low power. Kluwer Academic Publishers, Dordrecht (2002)
Najm, F.: A Survey of Power Estimation Techniques in VLSI Circuits. IEEE Trans. on VLSI Systems 2(4) (December 1994)
Parker, K., McCluskey, E.: Probabilistic Treatment of General Combinational Networks. IEEE Trans. on Computer 24 (June 1975)
Costa, J., Monteiro, J., Devadas, S.: Switching Activity Estimation Using Limited Depth Reconvergent Path Analysis. In: ISLPED, Monterey, CA, USA, August (1997)
Schneider, P., Schlichtmann, U., Wurth, B.: Fast Power Estimation of Large Circuits. IEEE Design & Test of Computers (Spring 1996)
Marculescu, R., Marculescu, D., Pedram, M.: Probabilistic Modeling of Dependencies during Switching Activity Analysis. IEEE Trans. on CAD of ICs and Systems 17(2) (February 1998)
Theodoridis, G., Theoharis, S., Soudris, D., Goutis, C.: Switching Activity Estimation under Real-Gate Delay Using Timed Boolean Functions. IEE Proc. - Computers and Digital Techniques 147(6) (November 2000)
Bhanja, S., Ranganathan, N.: Cascaded Bayesian Inferencing for Switching Activity Esti-mation with Correlated Inputs. IEEE Trans. on VLSI Systems 12(12) (December 2004)
Agrawal, V., Sheth, S.: Mutually Disjoint Signals and Probability Calculation in Digital Circuits. In: Great Lakes Symposium on VLSI, Lafayette, LA, USA (February 1998)
Torroja, Y., Casado, F., Machado, F., Riesgo, T., de la Torre, E., Uceda, J.: Using a Simpli-fied Hardware Model to Analyse the Quality of VHDL Based Designs. In: DATE (User Forum), France (March 2000)
Torroja, Y., Casado, F., Machado, F., Riesgo, T., de la Torre, E., Uceda, J.: Ardid: A Tool and a Model for the Quality Analysis of VHDL Based Designs. In: Virtual Components: Design & Reuse. Kluwer, Dordrecht (2001)
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Machado, F., Riesgo, T., Torroja, Y. (2006). A Method for Switching Activity Analysis of VHDL-RTL Combinatorial Circuits. In: Vounckx, J., Azemard, N., Maurine, P. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2006. Lecture Notes in Computer Science, vol 4148. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11847083_63
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DOI: https://doi.org/10.1007/11847083_63
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-39094-7
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