Abstract
Asynchronous design is emerging as a practical alternative to synchronous design for both low power and high performance applications. Moreover, ASIC flows that support asynchronous design are becoming complete, including many that leverage existing front-end and back-end synchronous-oriented tools. This talk will review the different design styles and flows and highlight some of the on-going commercialization efforts in this area. Special attention will be paid to the single-track circuit families developed at USC that provide ultra high performance and low power characteristics. We will review the associated standard-cell libraries and flows that have been developed as well as the recent chip design efforts that demonstrate the benefits of this technology.
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© 2006 Springer-Verlag Berlin Heidelberg
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Beerel, P.A. (2006). Asynchronous Design for High-Speed and Low-Power Circuits. In: Vounckx, J., Azemard, N., Maurine, P. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2006. Lecture Notes in Computer Science, vol 4148. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11847083_66
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DOI: https://doi.org/10.1007/11847083_66
Publisher Name: Springer, Berlin, Heidelberg
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