Abstract
The main memory is one of the most energy-consuming components in several embedded system. In order to minimize this memory consumption, an architectural solution is recently adopted. It consists of multi-banking the addressing space instead of monolithic memory. The main advantage in this approach is the capability of setting individually banks in low power modes when they are not accessed, such that only the accessed bank is maintained in active mode. In this paper we investigate how this power management capability built into modern DRAM devices can be handled for real-time and multitasking applications. We aim to find, at system level design, both an efficient allocation of application’s tasks to memory banks, and the memory configuration that lessen the energy consumption: number of banks and the size of each bank. Results show the effectiveness of this approach and the large energy savings.
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Ben Fradj, H., Belleudy, C., Auguin, M. (2006). System Level Multi-bank Main Memory Configuration for Energy Reduction. In: Vounckx, J., Azemard, N., Maurine, P. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2006. Lecture Notes in Computer Science, vol 4148. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11847083_9
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DOI: https://doi.org/10.1007/11847083_9
Publisher Name: Springer, Berlin, Heidelberg
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