Abstract
This paper describes a control system processor architecture based on ΔΣ modulation (ΔΣ-CSP). The ΔΣ-CSP uses 1-bit processing which is a new concept in digital control to remove multi-bit multiplications. A simple conditional-negate-and-add (CNA) unit is proposed for most operations of control laws. For this reason, the targeted processor is small and very fast, making it ideal for embedded real-time control applications. The ΔΣ-CSP has been implemented as a VLSI hard macro in a high-performance 0.13μm silicon process. Results show that it compares very favorably to other digital processors in terms of area and clock frequency.
Preview
Unable to display preview. Download preview PDF.
Similar content being viewed by others
References
Candy, J.C.: Oversampling delta-sigma data converters: theory, design, and simulation. Institute of Electrical and Electronics Engineers, New York (1992)
Kershaw, S., Summerfield, S., Sandler, M., Anderson, M.: Realisation and implementation of a Sigma-Delta bitstream FIR filter. In: IEE Proc.-Circuits Devices Syst., vol. 143, pp. 267–273 (October 1996)
Kershaw, S.: Sigma-Delta Bitstream Processors Analysis and Design. PhD thesis, Kings College (July 1996)
Angus, J.A.S., Draper, S.: An improved method for directly filtering σ − δ audio signals. In: Proc. AES 104th convention, Amsterdam, The Netherlands (1998)
Wu, X., Goodall, R.: One-bit processing for digital control. IEE proceedings on Control Theory Applications (August 2005)
Ardalan, S.H., Paulos, J.J.: An analysis of nonlinear behavior in delta-sigma modulators. IEEE Transactions on Circuits and Systems 34, 593–604 (1987)
Liu, B.: Effect of finite wordlength on the accuracy of digital filters — a review. IEEE Transactions on Circuit Theory CT-18, 670–677 (1971)
Agarwal, R.C., Burrus, C.S.: New recursive digital filter structures having very low sensitivity and roundoff noise. IEEE Trans. Circuits Syst. CAS-22(12) (1975)
Goodall, R.M., Brown, D.S.: High speed digital controllers using an 8-bit microprocessor. Software and Microsystems 4, 109–116 (1985)
Jones, S., Goodall, R., Gooch, M.: Targeted processor architectures for high-performance controller implementation. Control Engineering Practice 6, 867–878 (1998)
Parra, R.A.C.: On the design and implementation of a control system processor. PhD thesis, Loughborough University (2001)
Forsythe, W., Goodall, R.M.: Digital control: Fundamentals, theory and practice. McGraw-Hill, USA (1991)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2006 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Wu, X., Chouliaras, V., Nunez-Yanez, J., Goodall, R., Vladimirova, T. (2006). A Novel Processor Architecture for Real-Time Control. In: Jesshope, C., Egan, C. (eds) Advances in Computer Systems Architecture. ACSAC 2006. Lecture Notes in Computer Science, vol 4186. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11859802_22
Download citation
DOI: https://doi.org/10.1007/11859802_22
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-40056-1
Online ISBN: 978-3-540-40058-5
eBook Packages: Computer ScienceComputer Science (R0)