Abstract
Leakage power will exceed dynamic power in microprocessor as feature size shrinks, especially for on-chip caches. Besides developing low leakage process and circuit, how to control the leakage power in architectural level is worth to be studied. In this paper, a PDSR (Periodically Drowsy Speculatively Recover) algorithm and its extended version with adaptivity are proposed to optimize instruction cache leakage power dissipation. SPEC CPU2000 simulation results show that, with negligible performance loss, PDSR can aggressively decrease leakage power dissipation of instruction cache. Compared with other existing methods, PDSR and adaptive PDSR achieve more satisfying and more robust energy efficiency.
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Zhang, C., Zhou, H., Zhang, M., Xing, Z. (2006). An Architectural Leakage Power Reduction Method for Instruction Cache in Ultra Deep Submicron Microprocessors. In: Jesshope, C., Egan, C. (eds) Advances in Computer Systems Architecture. ACSAC 2006. Lecture Notes in Computer Science, vol 4186. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11859802_62
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DOI: https://doi.org/10.1007/11859802_62
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-40056-1
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