Abstract
This paper proposes a DiffServ-over-MPLS Traffic Engineering (TE) architecture and describes the implementation of its functional blocks on Intel IXP2400 Network Processor using Intel IXA SDK 4.1 framework. We propose fast and scalable 6-tuple range-match classifier, which allows traffic policing procedures to operate on per-flow level, and a scalable low-jitter Deficit Round Robin (DRR) scheduler that can provide bandwidth guarantees on LSP level. The proposed DiffServ-over-MPLS TE functional blocks have been implemented on Intel IXDP2400 platform for up to 4,096 flows mapped to L-LSPs, and can handle an aggregated traffic rate of 2.4Gbps.
This research was supported by the MIC, under the ITRC support program supervised by the IITA.
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Siradjev, D., Gurin, I., Yoon, S.-H., Park, J.-K.: DiffServ-over-MPLS TE on IXDP2400. YUANTL-TR-06-NP-DSMPLS-01 (July 2006)
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Siradjev, D., Gurin, I., Kim, YT. (2006). Scalable DiffServ-over-MPLS Traffic Engineering with Per-flow Traffic Policing. In: Kim, YT., Takano, M. (eds) Management of Convergence Networks and Services. APNOMS 2006. Lecture Notes in Computer Science, vol 4238. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11876601_53
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DOI: https://doi.org/10.1007/11876601_53
Publisher Name: Springer, Berlin, Heidelberg
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