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A Digital Hardware Architecture of Self-Organizing Relationship (SOR) Network

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Neural Information Processing (ICONIP 2006)

Part of the book series: Lecture Notes in Computer Science ((LNTCS,volume 4234))

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Abstract

This paper describes a new algorithm of self-organizing relationship (SOR) network for an efficient digital hardware implementation and also presents its digital hardware architecture. In SOR network, the weighted average of fuzzy inference takes heavy calculation cost. To cope with this problem, we propose a fast calculation algorithm for the weighted average using only active units. We also propose a new generating technique of membership function by representing its width on power-of-two, which suits well with the digital hardware bit-shift process. The proposed algorithm is implemented on FPGA with massively parallel architecture. The experimental result shows that the proposed SOR network architecture has a good approximation ability of nonlinear functions.

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© 2006 Springer-Verlag Berlin Heidelberg

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Tamukoh, H., Horio, K., Yamakawa, T. (2006). A Digital Hardware Architecture of Self-Organizing Relationship (SOR) Network. In: King, I., Wang, J., Chan, LW., Wang, D. (eds) Neural Information Processing. ICONIP 2006. Lecture Notes in Computer Science, vol 4234. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11893295_129

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  • DOI: https://doi.org/10.1007/11893295_129

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-46484-6

  • Online ISBN: 978-3-540-46485-3

  • eBook Packages: Computer ScienceComputer Science (R0)

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