Abstract
Current parallel architectures are not optimized to all different kinds of applications since they can vary in requirements and resource needs. An ideal system to attend different applications should be able to fit their different characteristics and resource needs and to improve application performance. Our objective is to design and to develop a system architecture that can be reconfigured to fulfill many kinds of the application requirements and run with a reduced communication overhead. Our main goal is a new Reconfigurable Chip-MultiProcessor architecture that improves adaptability to have better performance, regardless of the application requirements. Our results and its analysis show that our architecture provides greater flexibility and scalability and still obtains performance gain over one multiprocessor architecture. Our main contribution is a Reconfigurable Chip-Multiprocessor architecture, composed of reconfigurable processing, storage and interconnection elements.
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Boa, R.F., da Penha, D.O., Amaral, A.M., de Souza, M.O.S., da Silva Martins, C.A.P., Ekel, P.Y. (2006). RCMP: A Reconfigurable Chip-Multiprocessor Architecture. In: Min, G., Di Martino, B., Yang, L.T., Guo, M., Rünger, G. (eds) Frontiers of High Performance Computing and Networking – ISPA 2006 Workshops. ISPA 2006. Lecture Notes in Computer Science, vol 4331. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11942634_11
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DOI: https://doi.org/10.1007/11942634_11
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-49860-5
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