Abstract
In this work, we propose a novel dual-execution modes processor, named FunctionalAssignment RegisterMachine (FaRM), which supports both Queue and Stack execution models in a single and simple processor core.
The hardware elements, instruction formats and the major hardware components of the processor are presented in sufficient detail. We also give a preliminary evaluation result of the designed processor. From our preliminary evaluation results, we found that FaRM processor achieves about 65MHz speed and can execute both Queue and Stack execution models correctly. We also found that the novel architecture is implemented without considerable additional hardware when compared with conventional architectures with similar hardware configurations.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Akanda, M.M., Abderazek, B.A., Sowa, M.: An Efficient Dynamic Switching Mechanism (DSM) for Hybrid Processor Architecture. In: Yang, L.T., Amamiya, M., Liu, Z., Guo, M., Rammig, F.J. (eds.) EUC 2005. LNCS, vol. 3824, pp. 77–86. Springer, Heidelberg (2005)
Radhakrishnan, R., Talla, D., John, L.K.: Allowing for ILP in an embedded Java processor. In: Proceedings of the 27th International Symposium on Computer Architecture, June 2000, pp. 294–305 (2000)
Sowa, M., Abderazek, B.A., Yoshinaga, T.: FARM Processor, Parallel Queue Processor Architecture Based on Produced order computation model. Int. Journal of Supercomputing, HPC 32(3), 217–229 (2005)
Schoeberl, M.: JOP: A Java Optimized Processor for Embedded Real-Time Systems, PhD thesis, Vienna University of Technology (2005)
Abderazek, B.A., Shigeta, S., Yoshinaga, T., Sowa, M.: On the Design of Register-Queue Based Processor Architecture (FARM-rq). LNCS, vol. 2745, pp. 248–262. Springer, Heidelberg (2003)
VijayKrishnan, N.: Issues in the Design of JAVA Processor Architecture, PhD dissertation, University of South Florida, Tampa, FL-33620 (December 1998)
Radhakrishnan, R., Vijaykrishnan, N., John, L., Sivasubramanium, A.: Architectural issues in java runtime systems, Tech. Rep. TR-990719, (1999)
Abderazek, B.A., Yoshinaga, T., Sowa, M.: High-Level Modeling and FPGA Prototyping of Produced Order Parallel Queue Processor Core. Journal of supercomputing 38(1), 3–15 (2006)
STRATIX devices: http://www.altera.com/products/devices/stratix/
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2006 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Akanda, M.M., Abderazek, B.A., Sowa, M. (2006). On the Design of a Dual-Execution Modes Processor: Architecture and Preliminary Evaluation. In: Min, G., Di Martino, B., Yang, L.T., Guo, M., Rünger, G. (eds) Frontiers of High Performance Computing and Networking – ISPA 2006 Workshops. ISPA 2006. Lecture Notes in Computer Science, vol 4331. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11942634_5
Download citation
DOI: https://doi.org/10.1007/11942634_5
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-49860-5
Online ISBN: 978-3-540-49862-9
eBook Packages: Computer ScienceComputer Science (R0)