Abstract
In this paper we present the architecture and implementation of a hardware NIC scheduler to guarantee QoS on servers for high speed LAN/SAN. Our proposal employs a programmable logic device based on an FPGA in order to store and update connection states, and to decide what data stream is to be sent next. The network architecture is connection-oriented and reliable, based on credit flow control. The architecture scales from 4 to 32 streams using a Xilinx Virtex 2000E. It supports links with speeds in the order of Gbps while, maintaining the delay and jitter constrains for the QoS streams.
This work was partially supported by the Spanish CICYT grant TIC2003-08154-C06 and the European FEDER program.
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Caminero, M.B.: Diseño de un Encaminador Orientado a Tráfico Multimedia en Entornos LAN. Phd. Thesis, Albacete (June 2002) (in Spanish)
Caminero, M.B., Carrión, C., Quiles, F.J., Duato, J., Yalamanchili, S.: A Cost-Effective Hardware Link Scheduling Algorithm for the Multimedia Router (MMR). In: Lorenz, P. (ed.) ICN 2001. LNCS, vol. 2094, p. 358. Springer, Heidelberg (2001)
Caminero, M.B., Carrión, C., Quiles, F.J., Duato, J., Yalamanchili, S.: Investigating switch scheduling algorithms to support QoS in the Multimedia Router (MMR). In: Proceedings, Workshop on Communication Architecture for Clusters (CAC 2002). IEEE Computer Society, Los Alamitos (2002)
Canseco, M., Claver, J.M., León, G., Vilata, I.: Primeras Experiencias en la implementación de un encaminador QoS sobre una FPGA. IV Jornadas de Computación Reconfigurable y Aplicaciones, Bellaterra (Spain) (September 2004) (in Spanish)
Chapell, S., Sullivan, C.: Handel-C for co-processing an co-design of field programmable systems on chip. In: Proceeding of the JCRA 2002 (2002)
Claver, J.M., Carrión, M.C., Canseco, M., Caminero, M.B., Quiles, F.J.: A New Hardware Efficient Link Scheduling Algorithm to Guarantee QoS on Clusters. In: Cunha, J.C., Medeiros, P.D. (eds.) Euro-Par 2005. LNCS, vol. 3648, pp. 1046–1056. Springer, Heidelberg (2005)
Celoxica: RC1000 Software reference manual (2001)
Gaughan, P.T., Yalamanchili, S.: Adaptive routing protocols for direct multiprocessor networks. IEEE Computer (May 1993)
Krishnamurthy, R., Yalamanchili, S., Schwan, K., West, R.: Architecture and Hardware for Scheduling Gigabit Packet Streams. In: Proceedings of the 10th Symposium on High Performance Interconnects Hot Interconnects (HotI 2002) (2002)
Martínez, A., Alfaro, F.J., Sánchez, J.L., Duato, J.: Providing Full QoS Support in Clusters Using Only Two VCs at the Switches. In: XII IEEE International Conference on High Performance Computing (HiPC), Goa (India) (December 2005)
Rexford, J.L., Greenberg, A.G., Bonomi, F.G.: Hardware-efficient fair queuing architectures for High speed networks. In: Proceedings of the IEEE INFOCOM 1996, San Francisco (March 1996)
Shanley, T.: Infiniband Network Architecture. Addison-Wesley, Reading (2003)
Moon, S., Rexford, J., Shin, K.: Scalable hardware priority queue architectures for high speed packet switches. IEEE Trans. on Computers 49(11), 1215–1227 (2000)
West, R., Poellabauer, C.: Analysis of a Window-Constrained Scheduler for Real-time and Best-Effort Packet Streams. In: Proceedings of the 21st Real Time Systems Symposium (November 2000)
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Claver, J.M., Canseco, M., Agustí, P., León, G. (2006). A Hardware NIC Scheduler to Guarantee QoS on High Performance Servers. In: Guo, M., Yang, L.T., Di Martino, B., Zima, H.P., Dongarra, J., Tang, F. (eds) Parallel and Distributed Processing and Applications. ISPA 2006. Lecture Notes in Computer Science, vol 4330. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11946441_13
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DOI: https://doi.org/10.1007/11946441_13
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