Abstract
According to VLSI theory, [logn, √n] is the range of computation times for which there may exist an AT2-optimal multiplier of n-bit integers. Such networks were previously known for the time range [Ω(log2n), 0(√n)]; in this paper we settle this theoretical question, by exhibiting a-class of AT2-optimal multipliers with computation times [Ω(logn), 0(n1/2)]. Our designs are based on the DFT on a Fermat ring, whose elements are represented in a redundant radix-4 form to ensure 0(1) addition time.
This work was supported by the National Science Foundation under Grants MCS-81-05552 and ECS-81-06939; additional support was provided by Deutsche Forschungsgemeinschaft SFB 124, VLSI — Entwurf und Parallelität.
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Mehlhorn, K., Preparata, F.P. (1984). Area-time optimal vlsi integer multiplier with minimum computation time. In: Paredaens, J. (eds) Automata, Languages and Programming. ICALP 1984. Lecture Notes in Computer Science, vol 172. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-13345-3_31
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DOI: https://doi.org/10.1007/3-540-13345-3_31
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