Abstract
A hardware simulator of PIM-R (Reduction-Based Parallel Inference Machine) has been developed. Eight MC68000 single board computers and shared storage operate as the inference modules and the network, respectively. In order to realize high simulation rate, an event-driven method is introduced. ”Queens” program and ”Quicksort” program were executed on the simulator. The results show that a PIM-R architecture can effectivity utilize the parallelism in Prolog/Concurrent Prolog programs.
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© 1986 Springer-Verlag Berlin Heidelberg
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Sugie, M. et al. (1986). Hardware simulator of Reduction-Based Parallel Inference Machine PIM-R. In: Wada, E. (eds) Logic Programming '85. LP 1985. Lecture Notes in Computer Science, vol 221. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-16479-0_2
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DOI: https://doi.org/10.1007/3-540-16479-0_2
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Publisher Name: Springer, Berlin, Heidelberg
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Online ISBN: 978-3-540-39820-2
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