Skip to main content
SpringerLink
Log in

Linear algorithms for two CMOS layout problems

  • Conference paper
  • First Online:
VLSI Algorithms and Architectures (AWOC 1986)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 227))

Included in the following conference series:

Abstract

[UC,BNR] formulate a linear layout problem for static CMOS gates and give partial solutions of the problem. [O] reformulates the problem in two ways for dynamic CMOS cells and gives partial solutions. We give complete solutions to both problems formulated by [O] by giving linear algorithms.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Log in via an institution

Institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. Brayton, R.K./Brenner, N.L./Chen, C.L./DeMicheli, G./ McMullen, C.T. & Otten, R.H.J.M.: The Yorktown Silicon Compiler. ISCAS '85, Kyoto, Japan, June 1985

    Google Scholar 

  2. Brayton, R.K./Chen, C.L./Otten, R.H.J.M. & Yamour, Y.Y.: Automatic Implementation Of Switching Functions As Dynamic CMOS Circuits. CICC 1984

    Google Scholar 

  3. Bruss, A./Nair, R. & Reif, J.: Linear Time Algorithms For Optimal CMOS Layout. IBM, Thomas J. Watson Research Center, Yorktown Heights, New York, Research Report, Dec. 1983

    Google Scholar 

  4. Even, S.: Graph Algorithms. Pitman, London 1979

    Google Scholar 

  5. Ibaraki, T. & Muroga, S.: Minimization of Switching Networks Using Negative Functions. Department of Computer Science, University of Illinois, Urbana, Ill., Report 309, February 1969

    Google Scholar 

  6. Muroga, S: Logic Design and Switching Theory. John Wiley, New York 1979

    Google Scholar 

  7. Mead, C. & Conway, L.: Introduction To VLSI-Systems. Addison Wesley 1980

    Google Scholar 

  8. Müller, R.: Lineare Algorithmen für ein Layoutproblem für CMOS-Gatter. Diploma thesis, University of Paderborn, Paderborn, West Germany, January 1986

    Google Scholar 

  9. Nakamura, K./Tokura, N. & Kasani, T.: Minimal Negative Gate Networks. IEEE Trans. Comput., Jan 5–11, 1972

    Google Scholar 

  10. Otten, R.H.J.M.: Layout Compilation From A Functional Description. Overhead slides of a talk at IBM Europe Institute, Lech, Austria 1985

    Google Scholar 

  11. Otten, R.H.J.M.: personal communication, June 1985

    Google Scholar 

  12. Uehara, T. & van Cleemput, W.M.: Optimal Layout of Functional Arrays. IEEE Trans. Comput., pp 305–312, May 1981

    Google Scholar 

  13. Valdes, J.: Parsing Flowcharts And Series-Parallel Graphs. Ph.D. dissertation, Department Of Computer Science, Stanford University, Dec. 1978

    Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Fachbereich 17, University of Paderborn, 4790, Paderborn, West Germany

    Rolf Müller & Thomas Lengauer

Authors
  1. Rolf Müller
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Thomas Lengauer
    View author publications

    You can also search for this author in PubMed Google Scholar

Editor information

Filia Makedon Kurt Mehlhorn T. Papatheodorou P. Spirakis

Rights and permissions

Reprints and permissions

Copyright information

© 1986 Springer-Verlag Berlin Heidelberg

About this paper

Cite this paper

Müller, R., Lengauer, T. (1986). Linear algorithms for two CMOS layout problems. In: Makedon, F., Mehlhorn, K., Papatheodorou, T., Spirakis, P. (eds) VLSI Algorithms and Architectures. AWOC 1986. Lecture Notes in Computer Science, vol 227. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-16766-8_11

Download citation

  • DOI: https://doi.org/10.1007/3-540-16766-8_11

  • Published:

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-16766-2

  • Online ISBN: 978-3-540-38746-6

  • eBook Packages: Springer Book Archive

Publish with us

Policies and ethics

Search

Navigation