Abstract
The single-chip, high-performance signal processor design described in this paper departs from existing processor designs both in the way it is organized and the manner in which it performs computations. Major emphasis is placed on the exploitation of parallelism and pipelining inherently present in signal processing functions, and on novel processing architecture that allows mapping of high-level computations, such as Fast-Fourier-Transforms (FFT), directly into hardware. The single-chip design is based on a 2μ-CMOS technology, utilizes bit-serial arithmetic and is externally provided with appropriately organized first-in/first-out (FIFO) memory. The processor is suitable for use in real-time situations such as radar, sonar, and seismic data processing.
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© 1986 Springer-Verlag Berlin Heidelberg
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Kanopoulos, N., Marinos, P.N. (1986). A high-performance single-chip vlsi signal processor architecture. In: Makedon, F., Mehlhorn, K., Papatheodorou, T., Spirakis, P. (eds) VLSI Algorithms and Architectures. AWOC 1986. Lecture Notes in Computer Science, vol 227. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-16766-8_15
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DOI: https://doi.org/10.1007/3-540-16766-8_15
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