Skip to main content
SpringerLink
Log in

AT2-optimal galois field multiplier for VLSI

  • Conference paper
  • First Online:
VLSI Algorithms and Architectures (AWOC 1986)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 227))

Included in the following conference series:

Abstract

For every prime p, there are AT2-optimal VLSI multipliers for Galois fields GF(pn) in standard notation. In fact, the lower bound AT2 = Ω(n2) is matched for every computation time T in the range [Ω(log n), 0(√n)]. Similar results hold for variable primes p too. The designs are based on the DFT on a structure similar to Fermat rings. For p=2 the DFT uses 3l-th instead of 2l-th rotts of unity.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Log in via an institution

Institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  • Abelson, H. and Andreae, P. (1980), Information transfer and area-time tradeoffs for VLSI multiplication, Comm. ACM 23, No. 1, 20–22.

    Google Scholar 

  • Aho, A.V., Hopcroft, J.E. and Ullman, J.D. (1974), "The Design and Analysis of Computer Algorithms", Addison-Wesley, Reading, Mass.

    Google Scholar 

  • Beame, P.W., Cook, S.A. and Hoover, H.J. (1984), Log Depth Circuits for Division and Related Problems, 25th FOCS, (IEEE Symp.), 1–6.

    Google Scholar 

  • Berlekamp, E.R. (1968), "Algebraic Coding Theory", McGraw-Hill, New York.

    Google Scholar 

  • Brent, R.P. and Kung, H.T. (1981), The chip complexity of binary arithmetic, J. Assoc. Comput. Mach. 28, 521–534.

    Google Scholar 

  • Fürer, M. (1985), in preparation.

    Google Scholar 

  • Kannan, R., Miller, R. and Rudolph, L. (1984), Sublinear Parallel Algorithm for Computing the Greatest Common Divisor of Two Integers, 25th FOCS, 7–11.

    Google Scholar 

  • Karazuba, A. and Ofman, Y. (1962), Multiplication of multidigit numbers on automata, Dokl. Akad. Nauk SSSR 145, 293–294.

    Google Scholar 

  • Knuth, D.E. (1981), "The Art of Computer Programming", Vol. 2: Semi-numerical Algoriths, Addison-Wesley, Reading, Mass., 2nd ed.

    Google Scholar 

  • Lengnauer, T. and Mehlhorn, K. (1983), VLSI complexity theory, efficient VLSI algorithms and the HILL design system, in "The International Professorship in Computer Science: Algorithmics for VLSI" (Trullemans, Ed.), Academic Press, New York, in press.

    Google Scholar 

  • van Lint, J.H. (1971), "Coding Theory", Springer LN in Math. 201, Berlin.

    Google Scholar 

  • Luk, W.K. and Vuillemin, J.E. (1983), "Recursive Implementation of Optimal Time VLSI Integer Multipliers", VLSI 83, Trondheim, Norway September.

    Google Scholar 

  • MacWilliams, F.J. and Sloane, N.J.A. (1978), "The Theory of Error-Correcting Codes", North-Holland, Amsterdam.

    Google Scholar 

  • Mehlhorn, K. (1984), AT2-optimal VLSI Integer Division and Integer Square Rooting, Integration 2, 163–167.

    Google Scholar 

  • Mehlhorn, K. and Preparata, F.P. (1983), Area-Time Optimal VLSI Integer Multiplier with Minimum Computation Time, Information and Control 58, 137–156.

    Google Scholar 

  • Mehlhorn, K. and Preparata, F.P. (1985), Area-Time Optimal Division for T=Ω(log n)1+ɛ), TR 05/1985, Sonderforschungsbericht, Univ. of Saarbrücken.

    Google Scholar 

  • Preparata, F.P. (1983), An Area-Time Optimal Mesh-Connected Multiplier of Large Integers, IEEE. Trans. Comput. C-32, No. 2, 194–198.

    Google Scholar 

  • Preparata, F.P. and Vuillemin, J. (1981a), The Cube-Connected-Cycles: A Versatile Network for Parallel Computation, Comm. ACM 24, No. 5, 300–309.

    Google Scholar 

  • Preparata, F.P. and Vuillemin, J. (1981b), Area-Time Optimal VLSI Networks for Computing Integer Multiplication and Discrete Fourier Transform, in "Proceedings, I.C.A.L.P., Haifa, Israel", 29–40.

    Google Scholar 

  • Reif, J. (1983), Logarithmic Depth Circuits for Algebraic Functions, 24th FOCS, 138–143.

    Google Scholar 

  • Schönhage, A. (1976), Schnelle Multiplikation von Polynomen über Körpern der Charakteristik 2, Acta Informatica 7, 395–398.

    Google Scholar 

  • Schönhage, A. and Strassen V., (1971), Schnelle Multiplikation grosser Zahlen, Computing 7, 281–292.

    Google Scholar 

  • Wang, C.C., Truong, T.K., Shao, H.M., Deutsch, L.J., Omura, J.K. and Reed, I.S. (1985), VLSI Architectures for Computing Multiplications and Inverses in GF(2m), IEEE Transaction on Computers, C-34, 709–717.

    Google Scholar 

  • Yao, A.C. (1981), The Entropic Limitations on VLSI Computations, 13th STOC (ACM Symposium), 308–311.

    Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Institut für Angew. Mathematik, Universität Zürich, CH-8001, Zürich, Switzerland

    Martin Fürer

  2. FB Angew. Math. und Informatik, Universität des Saarlandes, D-6600, Saarbrücken, Germany

    Kurt Mehlhorn

Authors
  1. Martin Fürer
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Kurt Mehlhorn
    View author publications

    You can also search for this author in PubMed Google Scholar

Editor information

Filia Makedon Kurt Mehlhorn T. Papatheodorou P. Spirakis

Rights and permissions

Reprints and permissions

Copyright information

© 1986 Springer-Verlag Berlin Heidelberg

About this paper

Cite this paper

Fürer, M., Mehlhorn, K. (1986). AT2-optimal galois field multiplier for VLSI. In: Makedon, F., Mehlhorn, K., Papatheodorou, T., Spirakis, P. (eds) VLSI Algorithms and Architectures. AWOC 1986. Lecture Notes in Computer Science, vol 227. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-16766-8_19

Download citation

  • DOI: https://doi.org/10.1007/3-540-16766-8_19

  • Published:

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-16766-2

  • Online ISBN: 978-3-540-38746-6

  • eBook Packages: Springer Book Archive

Publish with us

Policies and ethics

Search

Navigation