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Specification and properties of a cache coherence protocol model

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Advances in Petri Nets 1987 (APN 1986)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 266))

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Abstract

This paper describes a cache coherence protocol for an architecture composed of several processors, each with their own local cache, connected via a switching structure to a shared memory itself split into several modules managed by independent controllers. The protocol prevents processors from simultaneously modifying their respective copies and always provides a processor requiring a copy of a memory location with the most up-to-date version. A top down description and modeling of the protocol is given using Predicate/Transition nets. This modeling allows to formally describe the complex synchronizations of this protocol. Then invariants are directly obtained without unfolding the Predicate/Transition net. They are the basis for studying behavioral properties.

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Authors and Affiliations

  1. Université Paris VI - C.N.R.S. (M.A.S.I. and PRC - C3/Algorithmes répartis), 4 Place Jussieu, F75252, Paris Cedex 05

    C. Girault, C. Chatelain & S. Haddad

Authors
  1. C. Girault
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  2. C. Chatelain
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  3. S. Haddad
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Editor information

Grzegorz Rozenberg

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© 1987 Springer-Verlag Berlin Heidelberg

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Girault, C., Chatelain, C., Haddad, S. (1987). Specification and properties of a cache coherence protocol model. In: Rozenberg, G. (eds) Advances in Petri Nets 1987. APN 1986. Lecture Notes in Computer Science, vol 266. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-18086-9_17

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  • DOI: https://doi.org/10.1007/3-540-18086-9_17

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  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-18086-9

  • Online ISBN: 978-3-540-47743-3

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