Abstract
We propose a hardware unification array consisting of k × n fourconnected unification units to be used to speed up the process of finding suitable bindings for common variables among the predicates in a logic program. Four different algorithms (SIMPLEX, PCC, PwFLP and CP) to perform unification in the array are presented and their performances compared. The final level of unification in scheduling multiple arrays is found to be the most expensive, deserving the highest degree of hardware support.
Preview
Unable to display preview. Download preview PDF.
References
T. Moto-oka and H. Stone, "Fifth-Generation Computer Systems: a Japanese Project", IEEE Computer, (March 1984), pp. 6–13.
W.F. Clocksin and C.S. Mellish, Programming in Prolog, (1981), Springer-Verlag.
J.S. Conery and D.F. Kibler, "Parallel Interpretation of Logic Programs", Proceedings of 1981 Conference on Functional Programming Languages and Computer Architectures, (1981), pp. 163–170.
J.A. Robinson, "A Machine-Oriented Logic Based on the Resolution Principle, JACM, 12(1), pp. 23–41.
Y. Shobatake and H. Aiso, "A Unification Processor Based on Uniformly Structured Cellular Hardware", 13th Annual International Symposium on Computer Architecture, pp. 140–148.
T.P. Dobry, et. al., "Performance Studies of Prolog Machine Architectures", 12th International Symposium on Computer Architecture, pp. 180–190.
R. Nakazaki, et. al., "Design of a High Speed Prolog Machine (HPM)", 12th International Symposium on Computer Architecture, pp. 191–197.
P. Robinson, "The SUM: an AI Coprocessor", BYTE, (June, 1985), pp. 169–180.
H. Nakagawa, "AND Parallel Prolog with Divided Assertion Set", 1984 Symposium on Logic Programming, pp. 22–28.
Y.F. Shin, Parallel Processing of Production Systems: An Integrated Software and Hardware Approach, Ph.D. Dissertation, The University of Michigan, 1987.
Author information
Authors and Affiliations
Editor information
Rights and permissions
Copyright information
© 1988 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Shih, Y., Irani, K.B. (1988). Design and scheduling of mesh array of hardware unifiers for large-scale unification. In: Houstis, E.N., Papatheodorou, T.S., Polychronopoulos, C.D. (eds) Supercomputing. ICS 1987. Lecture Notes in Computer Science, vol 297. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-18991-2_39
Download citation
DOI: https://doi.org/10.1007/3-540-18991-2_39
Published:
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-18991-6
Online ISBN: 978-3-540-38888-3
eBook Packages: Springer Book Archive