Abstract
Reconfigurable Computing is a technique for executing algorithms directly on the hardware in order to accelerate and increase their performance. Recon-figurable hardware consists of programmed FPGA chips for working as specific purpose coprocessors. The algorithms to be executed are programmed by means of description hardware languages and implemented in hardware using synthesis tools. Reconfigurable Computing is very useful for processing high computational cost algorithms because the algorithms implemented in a specific hardware get greater performance than if they are processed by a general purpose conventional processor. So Reconfigurable Computing and parallel techniques have been applied on a genetic algorithm for solving the salesman problem and on a parallel evolutionary algorithm for time series predictions. The hardware implementation of these two problems allows a wide set of tools and techniques to be shown. In both cases satisfactory experimental performances have been obtained.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
E. Alba, M. Tomassini, “Parallelism and evolutionary algorithms”, IEEE Transactions on Evolutionary Computation, 6, IEEE Press, 2002, pp. 443–462.
C. Aporntewan, P. Chongstitvatana, “A Hardware Implementation of the Compact Genetic Algorithm”, IEEE Congress on Evolutionary Computation, IEEE 2001, pp. 624–629.
W. Banzhaf, “The ‘Molecular’ Traveling Salesman”, Biological Cybernetics 64, Springer-Verlag, 1990, pp. 7–14.
D.B. Fogel, “A Parallel Processing Approach to a Multiple Traveling Salesman Problem Using Evolutionary Programming”, Proc. 4th Annual Parallel Processing Symposium, Fullerton, CA, 1990, pp. 318–326.
D.B. Fogel, “Applying Evolutionary Programming to Selected Traveling Salesman Problems”, Cybernetics and Systems 24, Taylor-Francis, 1993, pp. 27–36.
P. Larrañaga, C.M.H. Kuijpers, R. Murga, I. Inza, S. Dizdarevic, “Genetic Algorithms for the Traveling Salesman Problem: A Review of Representations and Operators”, Artificial Intelligence Review 13, Springer, 1999, pp. 129–170.
P. Martin, “A Hardware Implementation of a Genetic Programming System using FPGAs and Handel-C”, Genetic Programming and Evolvable Machines 2(4), Springer, 2001, pp. 317–343.
E. Lawler, J. Karel, A. Rinnooy and D. Shmoys, The Traveling Salesman Problem, A Guided Tour of Combinatorial Optimization, Wiley, 1985.
Jünger, M., G. Reinelt and G. Rinaldi, “The Traveling Salesman Problem”, Annotated Bibliographies in Combinatorial Optimization, M. Dell’ Amico, F. Maffioli, S. Martello (eds.), Wiley, 1997, pp. 199–221.
E. Rich, K. Knight, Artificial Intelligence, McGraw-Hill, 1991.
D. Sima, T. Fountain, P. Kacsuk, Advanced Computer Architecture: A Design Space Approach, Addison-Wesley, 1998.
M.A. Vega, R,. Gutiérrez, J.M. Ávila, J.M. Sánchez, J.A. Gómez, “Genetic Algorithms Using Parallelism and FPGAs: The TSP as Case Study”, Proc. 2005 International Conference on Parallel Processing, IEEE Computer Society, 2005, pp. 573–579.
D. Whitley, T. Starkweather, D. Fuquay, “Scheduling Problems and Traveling Salesman: The Genetic Edge Recombination Operator”, Proc. 3rd International Conference on Genetic Algorithms, Los Altos, CA, USA, 1989, pp. 133–140.
D. Whitley, T. Starkweather, D. Shaner, “The Traveling Salesman and Sequence Scheduling: Quality Solutions Using Genetic Edge Recombination”, Handbook of Genetic Algorithms, Van Nostrand Reinhold, New York, USA, 1991, pp. 350–372.
B. Zeidman, Designing with FPGAs and CPLDs, CMP Books, 2002.
M.A. Vega, J.M. Sánchez, J.A. Gómez, ‘Guest Editors’ Introduction –Special Issue on FPGAs: Applications and Designs, Microprocessors and Microsystems, 28(5-6), Elsevier Science, 2004, pp. 193–196.
Gajski, D.D., Jianwen Zhu, Dmer, R., Gerstlauer, A., Shuqing Zhao, SpecC: Specification Language and Methodology, Springer, 2000.
G. Arnout, “SystemC standard”, Proceedings of the 2000 conference on Asia South Pacific design automation, ACM Press, 2000, pp. 573–578.
S. Vernalde, P. Schaumont, I. Bolsens, “An Object Oriented Programming Approach for Hardware Design”, Proceedings of the IEEE Computer Society Workshop on VLSI ′99, IEEE Computer Society, 1999, pp. 68.
K. Ramamritham, K. Arya, “System Software for Embedded Applications”, Proceedings of the 17th International Conference on VLSI Design. IEEE Computer Society, 2004, pp. 22.
RC1000-PP Reference Manuals, Celoxica, 2001.
Maxfleld, C., The Design Warrior’s Guide to FPGAs: Devices, Tools and Flows, Elsevier Science, 2004.
Söderstrom, T. and Stoica, P., System Identification, Prentice-Hall, 1989.
Ljung, L., System Identification, Prentice-Hall. 1999.
J.A. Gómez, M.A. Vega, J.M. Sánchez, “Parametric Identification of Solar Series based on an Adaptive Parallel Methodology”, Journal of Astrophysics and Astronomy 26, 2005, pp 1–13.
Back, T., Fogel, D.B., Michalewicz, Z., Handbook of Evolutionary Computation, Oxford University Press, New York, 1997.
M.A. Vega, J.M. Sánchez, J.A. Gómez, “Advances in FPGA Tools and Techniques”, Microprocessors and Microsystems 29 (2-3), Elsevier Science, 2005, pp. 47–50.
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2006 Springer
About this chapter
Cite this chapter
Rodríguez, M.A., Pulido, J.A., Pérez, J.M., Criado, J.M., del Solar, M.R. (2006). Reconfigurable Computing and Parallelism for Implementing and Accelerating Evolutionary Algorithms. In: Nedjah, N., Mourelle, L.d., Alba, E. (eds) Parallel Evolutionary Computations. Studies in Computational Intelligence, vol 22. Springer, Berlin, Heidelberg . https://doi.org/10.1007/3-540-32839-4_4
Download citation
DOI: https://doi.org/10.1007/3-540-32839-4_4
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-32837-7
Online ISBN: 978-3-540-32839-1
eBook Packages: EngineeringEngineering (R0)