Abstract
This paper presents a simulation model of the Time-Triggered Protocol (TTP/C) based embedded computer system as a tool for evaluation of system capability to tolerate a chosen category of faults. The model, being written in ANSI-C, is portable and machine-independent. Its structure is modular and flexible, so that the system to be studied and the experiment setting can easily be changed. The functionality of this model is demonstrated on a set of fault injection experiments aimed mainly to evaluate the correctness of the TTP/C specification. These experiments were done within the EU/IST FIT (Fault Injection for Time triggered architecture) project solution.
The research was in part supported by a grant of 5th Framework Program Information Societies Technology: IST-1999-10748 Fault Injection for Time Triggered Architecture (FIT).
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Herout, P., Racek, S., Hlavička, J. (2002). Model-Based Dependability Evaluation Method for TTP/C Based Systems. In: Bondavalli, A., Thevenod-Fosse, P. (eds) Dependable Computing EDCC-4. EDCC 2002. Lecture Notes in Computer Science, vol 2485. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-36080-8_23
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DOI: https://doi.org/10.1007/3-540-36080-8_23
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