Abstract
In this paper, we present the digital chaotic cryptography implementation on FPGA. The system realization uses AR filter and modulo function as a non - linear component. The hardware implementation of FPGA-based which consumed 288 CLBs has been successfully developed for 24 bits fixed point system using 4-th order filter. The maximum clock frequency used in the experiment is 6.747 MHz.
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© 2002 Springer-Verlag Berlin Heidelberg
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Utami, D., Suwastio, H., Sumadjudin, B. (2002). FPGA Implementation of Digital Chaotic Cryptography. In: Shafazand, H., Tjoa, A.M. (eds) EurAsia-ICT 2002: Information and Communication Technology. EurAsia-ICT 2002. Lecture Notes in Computer Science, vol 2510. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-36087-5_28
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DOI: https://doi.org/10.1007/3-540-36087-5_28
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