Skip to main content

WRAPS Scheduling and Its Efficient Implementation on Network Processors

  • Conference paper
  • First Online:
High Performance Computing — HiPC 2002 (HiPC 2002)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 2552))

Included in the following conference series:

Abstract

Network devices in high-speed networks need to support a large number of concurrent streams with different quality of service (QoS) requirements. This paper introduces a new packet scheduling algorithm and its efficient implementation on the novel programmable network processor-Intel’s IXP1200. WRAPS algorithm is based on the observation of packet rates within a dynamic window. The window can move continuously or discretely as the system transmits packets. Cumulated packet rates in the window are utilized to predict the next incoming packet of the same flow and reserve resource for the transmission of later packets. The implementation on network processor considers both accuracy and efficiency. To expedite the calculation and avoid the high cost of maintaining an ordered list, we designed a time- slotted circular queue to achieve O(1) insertion and selection time. Our experiments on the real system show good performance in terms of scalability and flow interference avoidance.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 84.99
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 109.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. A. Parekh, A Generalized Processor Sharing Approach to Flow Control in Integrated Service Networks. PhD thesis MIT, Feb, 1992.

    Google Scholar 

  2. Jon C.R Bennett and Hui Zhang, “Hierarchical packet fair queueing algorithms”, In ACM SIGCOMM.96, pp 143–156, Aug 1996.

    Google Scholar 

  3. Jon C.R Bennett and Hui Zhang, “WF2Q: Worst-case fair weighted fair queueing”, In IEEE INFOCOMM.96, pp 120–128, Mar 1996.

    Google Scholar 

  4. M.R. Hashemi, A. Leon-Garcia, “A RAM-based generic packet switch with scheduling capability”, Broadband Switching Systems Proceedings, pp.155–163, Dec.1997

    Google Scholar 

  5. Richard West, Karsten Schwan, “Dynamic Window-Constrained Scheduling for Multimedia Applications,” Proceedings of the IEEE International Conference on Multimedia Computing and Systems (ICMCS), 1999.

    Google Scholar 

  6. P. Crowley, M.E. Fiuczynski, J. Baer, B.N. Bershad, “Characterizing processor architectures for Programmable Network Interfacess”, Proceedings of the 2000 International Conference on Supercomputing, http://citeseer.nj.nec.com/304624.html.

  7. Kang Li, J. Walpole, Dylan McNamee, Calton Pu and David C. Steere, “ A Rate-Matching Packet Scheduler for Real-Rate Applications”, Multimedia Computing and Networking (MMCN’01), January 2001

    Google Scholar 

  8. Victor Firoiu, Jim Kurose, Don Towsley. “Efficient Admission Control for EDF Schedulers”. In Proc. of the IEEE INFORCOM’97

    Google Scholar 

  9. L.Y. Zhang, J.W.S. Liu, Z. Deng, I. Philp, “Hierarchical Scheduling of Periodic Messages in an Open System”, Real-Time Systems Symposium,1999. Proceedings The 20th IEEE, 1999.

    Google Scholar 

  10. Rabindra P. Kar, “Implementing Rhealstone Real-Time Benchmark”, Dr. Dobb’s Journal, April 1990

    Google Scholar 

  11. “IXP 1200 Network Processor: Software Reference Manual”, Part No. 278306-005. Sep.2000.

    Google Scholar 

  12. “IXP 1200 Network Processor: Programmer’s Reference Manual”, Part No. 278304-006. September, 2000.

    Google Scholar 

  13. “IXP 1200 Network Processor: Development Tools User’s Guide”, Part No. 278302-005. October,2000.

    Google Scholar 

  14. Richard West and Karsten Schwan, “Dynamic Window-Constrained Scheduling for Multimedia Applications”, IEEE International Conference on Multimedia Computing and Systems, 1999.

    Google Scholar 

  15. Austen McDonald and Weidong Shi, “Intel IXP 1200 Howto”, Feb 11, 2001 http://www3-int.cc.gatech.edu/systems/reading/ixp/austen/

  16. Nicholas Malcolm, Wei Zhao, “Hard Real-Time Communication in Multiple-Access Networks”, http://citeseer.nj.nec.com/malcolm95hard.html, 1995.

  17. D. Saha, S. Mukherjee, and S. K. Tripathi, “Multirate Scheduling of VBR Video Traffic in ATM Networks”, IEEE J. of Selected Areas in Communications, Vol.15, No. 6, Aug. 1997

    Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Editor information

Editors and Affiliations

Rights and permissions

Reprints and permissions

Copyright information

© 2002 Springer-Verlag Berlin Heidelberg

About this paper

Cite this paper

Zhuang, X., Liu, J. (2002). WRAPS Scheduling and Its Efficient Implementation on Network Processors. In: Sahni, S., Prasanna, V.K., Shukla, U. (eds) High Performance Computing — HiPC 2002. HiPC 2002. Lecture Notes in Computer Science, vol 2552. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-36265-7_24

Download citation

  • DOI: https://doi.org/10.1007/3-540-36265-7_24

  • Published:

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-00303-8

  • Online ISBN: 978-3-540-36265-4

  • eBook Packages: Springer Book Archive

Publish with us

Policies and ethics