A Behavioral Synthesis Tool for Exploiting Fine Grain Parallelism in FPGAs

Abstract

This paper describes how fine grain parallelism can be exploited using a behavioral synthesis tool called AccelFPGA which reads in high-level descriptions of DSP applications written in MATLAB, and automatically generates synthesizable RTL models in VHDL or Verilog. The RTL models can be synthesized using commercial logic synthesis tools and place and route tools onto FPGAs. The paper describes how powerful directives are used to provide high-level architectural tradeoffs by exploiting fine grain parallelism, pipelining, memory mapping and tiling for the DSP designer. Experimental results are reported with the AccelFPGA version 1.4 compiler on a set of 8 MATLAB benchmarks that are mapped onto the Xilinx Virtex II FPGAs.